A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.

A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.

A method for forming a plurality of semiconductor devices on a plurality of semiconductor wafers includes forming an electrically conductive layer on a surface of a first semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the first semiconductor wafer and the first semiconductor wafer. The method further includes forming an electrically conductive layer on a surface of a second semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the second semiconductor wafer and the second semiconductor wafer. A material composition of the electrically conductive layers formed on the first and second semiconductor wafers are selected based on a value of the physical property of the first and second semiconductor wafers, respectively. The material composition of the electrically conductive layers formed on the first and second semiconductor wafers are different.

A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.

A power integrated circuit includes a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a first portion of the semiconductor layer with a channel being formed in a first body region. The power integrated circuit includes a first deep diffusion region formed in the first deep well under the first body region and in electrical contact with the first body region and a second deep diffusion region formed in the first deep well under the drain drift region and in electrical contact with the first body region. The first deep diffusion region and the second deep diffusion region together form a reduced surface field (RESURF) structure in the LDMOS transistor.

A complementary metal oxide semiconductor (CMOS)-integrated junction field effect transistor (JFET) has reduced scale and reduced noise. An exemplary JFET has a substrate layer of one dopant type with a gate layer of that dopant type disposed on the substrate, a depletion channel of a second dopant type disposed on the first gate layer, and a second gate layer of the first dopant type disposed on the depletion channel and proximate a surface of the transistor. The second gate layer can separate the depletion channel from the surface, and the depletion channel separates the first gate layer from the second gate layer.

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaO.sub.X). The oxide target includes GaO.sub.X, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.

A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalls of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalls of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.