Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.

A method includes forming a first and a second gate dielectric on a first semiconductor channel region and a second semiconductor channel region overlapping the first semiconductor region, forming a first dipole film on the first gate dielectric, wherein the first dipole film comprises a first dipole dopant of a first type, and forming a second dipole film on the second gate dielectric. A drive-in process is performed to drive dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form a first transistor and a second transistor.

A method includes forming a lower semiconductor region, forming an upper semiconductor region overlapping the lower semiconductor region, forming a lower gate dielectric and an upper gate dielectric on the lower semiconductor region and the upper semiconductor region, respectively, forming a lower gate electrode on the lower gate dielectric and the upper gate dielectric, etching back the lower gate electrode, forming a gate isolation layer on the lower gate electrode that has been etched back, and forming an upper gate electrode over the gate isolation layer. The upper gate electrode is on the upper gate dielectric.

A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.

Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrating different materials into the channels for stacked transistor devices, for example in a CFET configuration, where the bottom device is an NMOS device and the top device is a PMOS device, or vice versa. Other embodiments may be described and/or claimed.

A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

A method of forming a complementary field-effect transistor (CFET) device includes: forming a plurality of channel regions stacked vertically over a fin; forming an isolation structure between a first subset of the plurality of channel regions and a second subset of the plurality of channel regions; forming a gate dielectric material around the plurality of channel regions and the isolation structure; forming a work function material around the gate dielectric material; forming a silicon-containing passivation layer around the work function material; after forming the silicon-containing passivation layer, removing a first portion of the silicon-containing passivation layer disposed around the first subset of the plurality of channel regions and keeping a second portion of the silicon-containing passivation layer disposed around the second subset of the plurality of channel regions; and after removing the first portion of the silicon-containing passivation layer, forming a gate fill material around the plurality of channel regions.

Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

A semiconductor device includes a plurality of first nanosheet fin structures located in a dense array region of a substrate. The semiconductor device further includes a plurality of first isolation trenches between adjacent first nanosheet fin structures of the plurality of first nanosheet fin structures. The plurality of first isolation trenches include: a first trench isolation layer, a protective liner formed on top of the first trench isolation layer, and a second trench isolation layer located above the protective liner. The protective liner separates the first trench isolation layer from the second trench isolation layer and the first trench isolation layer is more dense than the second trench isolation layer.

A Tunnel Field-Effect Transistor (TFET) device, an isolating layer over a substrate layer, a gate stack above the isolating layer, a source and a drain region over the isolating layer, a channel region underneath the gate stack, and a plurality of nanosheets in the channel region protruding from the source region. Each nanosheet of the plurality of nanosheets includes source region material encapsulated by a narrow band gap material.