H10D84/206

Circuit and method to enhance efficiency of memory

A method includes: providing a modulation circuit including a first resistive element, a second resistive element and a third resistive element; providing a memory array and a regulator connecting the modulation circuit to the memory array, wherein the regulator includes a transistor; determining an operation mode of the memory array; generating a first voltage at a drain terminal of the transistor, wherein the first voltage corresponds to a positive, negative zero temperature coefficient according to a first resistance ratio and a second resistance ratio; during a read operation, providing a first driving current to the memory array in response to the first voltage corresponding to the positive temperature coefficient; and during a write operation, providing a second driving current to the memory array in response to the first voltage corresponding to the negative temperature coefficient.

Semiconductor device

A semiconductor device includes; a bottom electrode on a substrate, a supporting pattern between the bottom electrode and an adjacent bottom electrode, a top electrode covering the bottom electrode and the supporting pattern, and a dielectric layer between the bottom electrode and the top electrode and between the supporting pattern and the top electrode. The bottom electrode may include a first portion including a seam and a second portion on the first portion, a top end of the second portion may be disposed at a height lower than an upper surface of the supporting pattern, and a portion of a bottom end of the second portion may be exposed to the seam.

Device including MIM capacitor and resistor

A method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.

Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
09806022 · 2017-10-31 · ·

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH STACKED ANALOG COMPONENTS IN BACK END OF LINE (BEOL) REGIONS
20170229391 · 2017-08-10 ·

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Two-dimensional large-area growth method for chalcogen compound, method for manufacturing CMOS-type structure, film of chalcogen compound, electronic device comprising film of chalcogen compound, and CMOS-type structure

Provided is a two-dimensional large-area growth method for a chalcogen compound, the method including: depositing a film of a transition metal element or a Group V element on a substrate; thereafter, uniformly diffusing a vaporized chalcogen element, a vaporized chalcogen precursor compound or a chalcogen compound represented by MX.sub.2+ within the film; and, thereafter, forming a film of a chalcogen compound represented by MX.sub.2 by forming the chalcogen compound represented by MX.sub.2 through post-heating.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
20170207295 · 2017-07-20 ·

A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.

FREQUENCY-VARIABLE TERAHERTZ OSCILLATOR AND METHOD FOR MANUFACTURING THE SAME
20170155361 · 2017-06-01 ·

A small-sized frequency-variable terahertz oscillator has a successive and large frequency-sweeping width even at a room temperature. The frequency-variable terahertz oscillator includes a slot antenna, a resonant tunneling diode and a varactor diode arranged parallel to each other along the slot antenna. The frequency-variable terahertz oscillator oscillates in a terahertz frequency range when the resonant tunneling diode and the varactor diode are separately applied with a direct voltage.

Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
09660015 · 2017-05-23 · ·

A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Method of inspecting by-products and method of manufacturing semiconductor device using the same

Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.