A semiconductor substrate includes a p-type substrate body, an n-type buried layer on the p-type substrate body, and a p-type semiconductor layer on the n-type buried layer. A DTI region penetrates through the p-type semiconductor layer and the n-type buried layer, and reaches the p-type substrate body. An n-type semiconductor region, which is a cathode region of a Zener diode, and a p-type anode region of the Zener diode are formed in the semiconductor layer. The p-type anode region includes a p-type first semiconductor region formed under the n-type semiconductor region, and a p-type second semiconductor region formed under the p-type first semiconductor region. A PN junction is formed between the p-type first semiconductor region and the n-type semiconductor region. An impurity concentration of the p-type second semiconductor region is higher than an impurity concentration of the p-type first semiconductor region.

A method for forming a plurality of semiconductor devices on a plurality of semiconductor wafers includes forming an electrically conductive layer on a surface of a first semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the first semiconductor wafer and the first semiconductor wafer. The method further includes forming an electrically conductive layer on a surface of a second semiconductor wafer so that a Schottky-contact is generated between the electrically conductive layer formed on the second semiconductor wafer and the second semiconductor wafer. A material composition of the electrically conductive layers formed on the first and second semiconductor wafers are selected based on a value of the physical property of the first and second semiconductor wafers, respectively. The material composition of the electrically conductive layers formed on the first and second semiconductor wafers are different.

A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

A semiconductor package in an embodiment includes a semiconductor device which has a first semiconductor element, a second semiconductor element, and a common first electrode between the first and second semiconductor elements. A second electrode is electrically connected to the first semiconductor element. A third electrode extends through the second semiconductor element and electrically connects to the first electrode. A fourth electrode is electrically connected to the second semiconductor element. A first terminal of the package is electrically connected to the third electrode. A second terminal of the package is electrically connected to the second electrode and the fourth electrode. An insulating material surrounds the semiconductor device.

Monolithic integration of low-capacitance p-n junctions and low-resistance p-n junctions (when conducting in reverse bias) is provided. Three epitaxial layers are used. The low-capacitance junctions are formed by the top two epitaxial layers. The low-resistance p-n junction is formed in the top epitaxial layer, and two buried structures at interfaces between the three epitaxial layers are used to provide a high doping region that extends from the low-resistance p-n junction to the substrate, thereby providing low resistance to current flow. The epitaxial layers are lightly doped as required by the low-capacitance junction design, so the buried structures are needed for the low-resistance p-n junction. The high doping region is formed by diffusion of dopants from the substrate and from the buried structures during thermal processing.

An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a rewiring layer opposed to the surface of the Si substrate, which includes terminal electrodes electrically connected to the pads. The rewiring layer includes a SiN protection film formed on the surface of the Si substrate to cover parts of the pads except regions in contact with openings (contact holes) formed in a resin layer, and the resin layer that is lower in dielectric constant than the SiN protection film, and formed between the SiN protection film and the terminal electrodes. Thus, provided is a semiconductor device which can reduce the generation of parasitic capacitance, and eliminates variation in parasitic capacitance generated.

A semiconductor structure includes: a substrate, having a cell region and a terminal region, and having a first surface, a second located in the terminal region, and a third surface located in the cell region, the second surface and the third surface being located at different levels; a first trench structure, located in the cell region, traversing the third surface to extend towards the first surface, including a first semiconductor material layer and a first oxide layer partially protruding from the third surface, and extending in a first direction parallel to the third surface; and a second trench structure, located in the cell region, including a second semiconductor material layer and a second oxide layer partially protruding from the third surface, and extending parallel to the first direction, wherein the third surface is provided with a doped region between the first trench structure and the second trench structure.

A method incudes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a second width greater than the first width is formed in a second region of a semiconductor substrate. A doped region is formed in a surface portion of the second plurality of fins to define an anode region of a diode. A junction is defined between the doped region and a cathode region of the second plurality of fins. A first contact interfacing with the anode region is formed.

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.