An integrated circuit comprising: a plurality of first gate electrodes extending in a second direction perpendicular to a first direction, wherein the plurality of first gate electrodes is in a first row that extends in the first direction; a first active pattern group comprising a plurality of first active patterns that extend in the first row in the first direction and intersecting the plurality of first gate electrodes; a plurality of second gate electrodes extending in the second direction in a second row that extends in the first direction; and a second active pattern group comprising a plurality of second active patterns extending in the second row in the first direction and intersecting the plurality of second gate electrodes, wherein ones of the plurality of first active patterns have different widths in the second direction, and the plurality of second active patterns have a first width in the second direction.

Gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, and methods of fabricating gate-all-around integrated circuit structures having differential nanowire thickness and gate oxide thickness, are described. For example, an integrated circuit structure includes a nanowire with an outer thickness and an inner thickness, the inner thickness less than the outer thickness. The nanowire tapers from outer regions having the outer thickness to an inner region having the inner thickness. A dielectric material is on and surrounding the nanowire such that a combined thickness of the nanowire and the dielectric material in the inner region is approximately the same as the outer thickness of the nanowire.

Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include first and second active patterns on a substrate. Each of the first and second active patterns may extend in a first direction. The first and second active patterns may be aligned along the first direction and may be separated by a first trench extending in a second direction. The first trench may define a first sidewall of the first active pattern. The semiconductor devices may also include a channel pattern including first and second semiconductor patterns stacked on the first active pattern, a dummy gate electrode on the channel pattern and extending in the second direction, and a gate spacer on one side of the dummy gate electrode, the one side of the dummy gate electrode being adjacent to the first trench. The gate spacer may cover a first sidewall of the first active pattern.

A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.

Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

A microelectronic structure that includes a stacked nanosheet FET transistor that includes an upper nanosheet transistor and a lower nanosheet transistor. The upper nanosheet transistor includes an upper source/drain and the upper source/drain includes an upper tip that is pointed in a first direction. The lower nanosheet transistor includes a lower source/drain and the lower source/drain includes a lower tip pointed in a second direction. The first direction is different than the second direction.

A semiconductor device includes a first transistor, a second transistor and an interconnect structure. The interconnect structure is disposed over the first transistor and the second transistor, wherein the interconnect structure includes a first conductive via electrically connecting a first source/drain contact of the first transistor to a second gate structure of the second transistor. The first conductive via is in contact with a top surface of the first source/drain contact and a side surface of the first source/drain contact.

A device comprising two transistors stacked along a main direction, the first transistor comprising channels stacked along the main direction and first source and drain contacts, the second transistor comprising channels stacked along the main direction and second source and drain contacts, wherein the first source (respectively drain) contact and the second source (respectively drain) contact are distinct and isolated from one another by a first gate dielectric layer and by a second gate dielectric layer. The invention also relates to a method for manufacturing the device.

A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.