The disclosed technology generally relates to a complementary field effect transistor (CFET) structure. In one aspect, the CFET structure includes at least one CFET element having a first transistor structure, and a second transistor structure which is arranged above the first transistor structure and which includes a source and/or drain structure. The CFET structure further includes a power rail arranged below the first transistor structure of the at least one CFET element, and a power routing line arranged above the second transistor structure of the at least one CFET element. The power routing line is electrically connected to the source and/or drain structure of the second transistor structure from the top. The at least one CFET element further has a tap connection structure which is arranged to electrically connect the power rail with the source and/or drain structure of the second transistor structure. The tap connection structure is arranged to bypass the first transistor structure on one side.

A method for forming a semiconductor structure includes forming a layer stack. The method also includes forming a gate structure on the layer stack, and forming at least one cavity by removing the at least one second sacrificial layer of the layer stack. The method further includes depositing a first dielectric material, and filling the at least one cavity with the first dielectric material. Further, the method includes providing a dielectric free gate surface, free from the first dielectric material. Furthermore, the method includes depositing a second dielectric material on the dielectric free gate surface. The second dielectric material is different from the first dielectric material.

An integrated circuit device may include a first transistor including first nanosheets having a first width in a first horizontal direction, a first gate structure surrounding the of first nanosheets and extending on a first side of the first nanosheets in a second horizontal direction perpendicular to the first horizontal direction, and first source/drain regions on opposite sides of the first nanosheets in the first direction; and a second transistor above the first transistor and including second nanosheets above the first nanosheets and having a second width equal to the first width in the first horizontal direction, a second gate structure surrounding the second nanosheets and on a second side of the second nanosheets in the second horizontal direction, and second source/drain regions on both sides of the second nanosheets in the first horizontal direction.

A static random access memory (SRAM) device includes a plurality of bit cells, each bit-cell including a first half-cell and a second half-cell, each half-cell including a first and a second complementary field-effect transistor (CFET) device. Each CFET device includes a bottom device and a top device stacked on top of the bottom device. The first CFET device includes a common gate shared by the bottom device and the top device and is configured as an inverter cross-coupled to the inverter of the other half-cell. The bottom device of the second CFET device is configured as a first pass-gate for a first port of the half-cell. The top device of the second CFET device is configured as a second pass-gate for a second port of the half-cell.

A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and/or a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and/or a p-MOS cavity in an exposed surface of the p-MOS region, wherein the cavity shaping process is configured to increase the surface area of the exposed surface of the n-MOS region or the p-MOS region. In some embodiments, the method includes performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

A semiconductor device includes a first active pattern including a first lower pattern and first sheet patterns spaced apart from the first lower pattern in a first direction, a first gate structure including first inner gates between the first lower pattern and a lowermost first sheet pattern of the first sheet patterns, and between each pair of adjacent first sheet patterns, the first inner gates extending in a second direction that intersects the first direction, where each of the first inner gates includes a first gate electrode and a first gate insulating film, first source/drain patterns on the first lower pattern and connected to the first sheet patterns, first inner spacers between the first source/drain patterns and the first inner gates, and first nitrogen build-up areas within the first inner spacers.

A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a method of fabricating a semiconductor structure comprises providing a FET structure disposed above a substrate, the FET structure comprising a vertical metal gate structure disposed between a pair of source/drain (S/D) epitaxial (EPI) structures and having a set of vertically-stacked, horizontal nanosheets extending through the vertical metal gate structure in the first horizontal direction to electrically connect the S/D EPI structures to each other. The method further comprises removing the substrate, removing the portion of vertical metal gate structure below the bottom-most nanosheet, removing at least enough of the bottom-most nanosheet to sever the its electrical conducting path between the S/D EPI structures, and filling the void created by the removed gate metal and nanosheet with a dielectric material that also covers the bottom surfaces of the S/D EPI structures.

An integrated circuit includes a set of transistors including a set of active regions, a set of power rails, a first set of conductors and a first conductor. The set of active regions extends in a first direction, and is on a first level. The set of power rails extends in the first direction and is on a second level. The set of power rails has a first width. The first set of conductors extends in the first direction, is on the second level, and overlaps the set of active regions. The first set of conductors has a second width. The first conductor extends in the first direction, is on the second level and is between the first set of conductors. The first conductor has the first width, electrically couples a first transistor of the set of transistors to a second transistor of the set of transistors.

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers is removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.

Semiconductor device structures are provided. The semiconductor device structure includes a semiconductor substrate with an original semiconductor surface and an active region, a STI region surrounding the active region, a transistor formed based on the active region and including a gate structure, a first conductive region, a second conductive region and a channel region between the first and second conductive regions, an interconnection structure extending beyond the transistor, and a connecting plug electrically connecting the interconnection structure to the first conductive region of the transistor. The first conductive region includes an epitaxial semiconductor material. The interconnection structure is disposed under the original semiconductor surface and within the STI region.