A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. The first-metal structure layout shapes are positioned on a first-metal vertical grid having at least eight first-metal gridlines. At least six contact structures are formed from substantially rectangular shaped contact structure layout shapes in physical and electrical contact with corresponding ones of at least six of the gate structures. A total number of first-transistor-type-only gate structures equals a total number of second-transistor-type-only gate structures within the region. At least four transistors of a first transistor type and at least four transistors of a second transistor type collectively form part of a logic circuit within the region.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

A first transistor has a gate electrode formed by a substantially linear portion of a first conductive structure. A second transistor has a gate electrode formed by a substantially linear portion of a second conductive structure. A third transistor has a gate electrode formed by a substantially linear portion of a third conductive structure. A fourth transistor has a gate electrode formed by a substantially linear portion of a fourth conductive structure. The substantially linear portions of the first, second, third, and fourth conductive structures extend in a first direction and are positioned in accordance with a gate pitch. Gate electrodes of the first and second transistors have a first size as measured in the first direction. Gate electrodes of the third and fourth transistors have a second size as measured in the first direction. The first size is at least two times the second size.

According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.

Embodiments of the invention relate to a metal configurable hybrid memory for use in integrated circuit designs for implementation in structured ASIC or similar platforms utilizing a base cell or standard cell. In accordance with certain aspects, a hybrid memory according to embodiments of the invention utilizes a fixed custom memory core and a customizable peripheral set of base cells. In accordance with these and further aspects, the hybrid memory can be specified using a macro, in which certain memory features (e.g. ECC, etc.) are implemented using the customizable peripheral set of base cells, and which may be selected or omitted from the design by the user. This enables the overall logic use for the memory to be optimized for a user's particular design. Unused logic in the customizable peripheral set of base cells can thus be freed for top-level logic use, thereby optimizing the design according to a user's functional and dimensional requirements and minimizing unnecessary waste of silicon area and power.

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

A first conductive structure forms a gate electrode of a first transistor of a first transistor type. A second conductive structure forms gate electrodes of both a second transistor of the first transistor type and a first transistor of a second transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms gate electrodes of both a third transistor of the first transistor type and a third transistor of the second transistor type. Gate electrodes of the first and second transistors of the first transistor type are separated by a fixed pitch, as are the gate electrodes of the second and third transistors of the second transistor type. The gate electrodes of the first transistor of the first transistor type and the second transistor of the second transistor type are separated by at least the fixed pitch.