A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

A semiconductor device includes a 2-input NOR decoder and an inverter that have six MOS transistors arranged in a line. The MOS transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicon layer on a surface of the planar silicon layer.

A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided.

A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

A SRAM cell comprising two PMOS transistors and two NMOS transistors is fabricated with CMOS process technology. The PMOS transistors are coupled to a supply voltage rail, a first storage node and a second storage node. The NMOS transistors are responsive to a word line and coupled to the first and the second storage nodes and a bit line pair. When the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage V.sub.stdf and a difference voltage (V.sub.DDV.sub.stdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period, where 0<V.sub.stdf<V.sub.DD.

A SRAM cell comprising two PMOS transistors and two NMOS transistors is fabricated with CMOS process technology. The PMOS transistors are coupled to a supply voltage rail, a first storage node and a second storage node. The NMOS transistors are responsive to a word line and coupled to the first and the second storage nodes and a bit line pair. When the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage V.sub.stdf and a difference voltage (V.sub.DDV.sub.stdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period, where 0<V.sub.stdf<V.sub.DD.