A library of a DFM-improved standard logic cells (including D flip-flop cells) that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.

A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s), and includes 13-CPP and 17-CPP D flip-flop cells, is disclosed, along with wafers, chips and systems constructed from such cells.

A terminal cell includes: third and fourth nanosheets formed at the same positions as first and second nanosheets, respectively, in the Y direction; and first and second dummy gate interconnects surrounding the peripheries of the third and fourth nanosheets, respectively, in the Y direction. Faces of the first and third nanosheets on one side in the Y direction are exposed from a first gate interconnect and the first dummy gate interconnect, respectively. Faces of the second and fourth nanosheets on one side in the Y direction are exposed from a second gate interconnect and the second dummy gate interconnect, respectively.

A terminal cell includes: third and fourth nanosheets formed at the same positions as first and second nanosheets, respectively, in the Y direction; and first and second dummy gate interconnects surrounding the peripheries of the third and fourth nanosheets, respectively, in the Y direction. Faces of the first and third nanosheets on one side in the Y direction are exposed from a first gate interconnect and the first dummy gate interconnect, respectively. Faces of the second and fourth nanosheets on one side in the Y direction are exposed from a second gate interconnect and the second dummy gate interconnect, respectively.