A rotor of an aircraft electric motor includes a shaft made of a first material, and a conductive assembly made of a second material different from the first material. The shaft includes a shoulder portion, the shoulder portion includes longitudinal notches. The notches include two contiguous notches radially superimposed in the shoulder portion, a first opening on a radially outer face of the shoulder portion, and a second opening connecting the two contiguous notches. The conductive assembly is a one-piece structure including a conductive bar that is positioned in one notch of the notches, and a skin that is fixed on the shoulder portion.

Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. The first-metal structure layout shapes are positioned on a first-metal vertical grid having at least eight first-metal gridlines. At least six contact structures are formed from substantially rectangular shaped contact structure layout shapes in physical and electrical contact with corresponding ones of at least six of the gate structures. A total number of first-transistor-type-only gate structures equals a total number of second-transistor-type-only gate structures within the region. At least four transistors of a first transistor type and at least four transistors of a second transistor type collectively form part of a logic circuit within the region.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.

An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts.

An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens.

An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts.

An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of chamfer shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of short-circuit failure modes, including at least one chamfer-short-related failure mode, one AACNT-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.