To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.

An array substrate, a preparation method thereof and a display apparatus are provided. The array substrate includes a plurality of pixel units distributed in a matrix and a plurality of scan lines and a plurality of data lines. Each pixel unit includes a display region and a device region. The display region includes a pixel electrode and a common electrode. The pixel electrode at least partially overlaps with the common electrode to form a first storage capacitor. The device region includes a drive transistor. The gate extends in a direction towards the display region to form a first extension portion; the drain extends in the direction towards the display region to form a second extension portion. The second extension portion is electrically connected to the pixel electrode. The first extension portion and the second extension portion overlap to form a second storage capacitor.

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

An array substrate and a method for manufacturing the same, and a display panel are provided. The array substrate includes a base substrate, gate lines, data lines, and multiple pixel units. The pixel unit includes a pixel electrode, a drive circuit, and a sharing electrode. The pixel electrode is electrically connected to the drive circuit. The drive circuit includes a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor. A source of the third thin-film transistor is connected to a drain of the second thin-film transistor. A drain of the third thin-film transistor is connected to the sharing electrode. The sharing electrode includes a first sharing electrode and a second sharing electrode electrically connected to the first sharing electrode. The projection of the first sharing electrode on the base substrate at least partially overlaps the projection of the pixel electrode on the base substrate.

The present disclosure provides a displaying backplane and a displaying device, and relates to the technical field of displaying. The displaying backplane includes: a substrate base plate; a first active layer and a second active layer that are provided on the substrate base plate, wherein the material of the first active layer and the second active layer is an oxide semiconductor, the first active layer has a first channel region and first no-channel regions, and the second active layer has a second channel region and second no-channel regions; a first grid insulating layer covering the first active layer and the second active layer; and a first grid and a second grid that are provided on the first grid insulating layer; wherein the oxygen-vacancy concentration of the first channel region is greater than the oxygen-vacancy concentrations of the first no-channel regions, the second no-channel regions and the second channel region.

An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.

An embodiment of the application discloses a panel and a manufacturing method thereof. In the panel, a thin-film transistor layer, a first conductive layer, a light-emitting diode (LED), and a second conductive layer are sequentially disposed on a substrate. The LED includes a first end and a second end. The first end is disposed on the first electrode. The second end is disposed on the second electrode. The second conductive layer includes a first conductive portion and a second conductive portion. The first conductive portion is electrically connected to the first end and the first electrode. The second conductive portion is electrically connected to the second end and the second electrode.

An oxide thin film transistor includes: a gate electrode, a metal oxide active layer and a source-drain metal layer, which are on a base substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; an electron transfer rate of the carrier transport layer is greater than an electron transfer rate of the carrier isolation layer. The first metal oxide layer includes a primary surface facing toward the base substrate and a primary surface away from the base substrate; the first metal oxide layer further includes a lateral surface around the primary surfaces; the second metal oxide layer covers the lateral surface of the first metal oxide layer.

The present disclosure provides a motherboard and a manufacturing method for the motherboard, the motherboard includes at least one display area, a periphery area surrounding the at least one display area, a plurality of test terminals, an electrostatic discharge line, a plurality of resistors and at least one thin film transistor. The plurality of test terminals are respectively electrically connected to the electrostatic discharge line through the plurality of resistors. At least one of the plurality of resistors includes an inorganic nonmetal trace. The at least one thin film transistor includes an active layer, and the inorganic nonmetal trace includes a same semiconductor matrix material as the active layer of the at least one thin film transistor.

An array substrate, a manufacturing method thereof, and a liquid crystal display panel are provided. The array substrate includes a substrate, a transparent oxide electrode, an interface protection layer, and a first insulating layer. The transparent oxide electrode is disposed on a side of the substrate. The interface protection layer is disposed on a side of the transparent oxide electrode away from the substrate. The first insulating layer is disposed on the interface protection layer.