A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer.

The disclosure provides a manufacturing method and a structure thereof of a TFT backplane. In the manufacturing method of the TFT backplane, after a polysilicon layer (3) is formed by implanting a induced ion solid-phase crystallization into an amorphous silicon layer (3), patterning the polysilicon layer using a half-tone mask to form an island active layer (4), and at the same time, etching a upper layer portion (31) with more implanted induced ions located in the middle portion of the island active layer (4) to form a channel region, retaining the upper layer portion (31) with more implanted induced ions located in two sides of the island active layer (4) to form a source/drain contact region, it not only reduces the number of masks, but also saves a process only for implanting doped ion into the source/drain contact region, thereby simplifying the process and reducing production cost.

An EL display device capable of performing clear multi-gradation color display and electronic equipment provided with the EL display device are provided, wherein gradation display is performed according to a time-division driving method in which the luminescence and non-luminescence of an EL element (109) disposed in a pixel (104) are controlled by time, and the influence by the characteristic variability of a current controlling TFT (108) is prevented. When this method is used, a data signal side driving circuit (102) and a gate signal side driving circuit (103) are formed with TFTs that use a silicon film having a peculiar crystal structure and exhibit an extremely high operation speed.

The disclosure provides a manufacturing method and a structure thereof of a TFT backplane. In the manufacturing method of the TFT backplane, after a polysilicon layer (3) is formed by implanting a induced ion solid-phase crystallization into an amorphous silicon layer (3), patterning the polysilicon layer using a half-tone mask to form an island active layer (4), and at the same time, etching a upper layer portion (31) with more implanted induced ions located in the middle portion of the island active layer (4) to form a channel region, retaining the upper layer portion (31) with more implanted induced ions located in two sides of the island active layer (4) to form a source/drain contact region, it not only reduces the number of masks, but also saves a process only for implanting doped ion into the source/drain contact region, thereby simplifying the process and reducing production cost.

A semiconductor device, comprising a base substrate, a buffer layer and a polysilicon layer film, wherein the base substrate, the buffer layer and the polysilicon layer film being laminated sequentially, and wherein regularly arranged first grooves being provided on a surface of the buffer layer contacting the polysilicon film; the polysilicon film being formed, by applying crystallization treatment, through an optical annealing process, to an amorphous silicon film on the buffer layer having regularly arranged first grooves.

It is an object of the invention to provide a technique to manufacture a display device with high image quality and high reliability at low cost with high yield. The invention has spacers over a pixel electrode layer in a pixel region and over an insulating layer functioning as a partition which covers the periphery of the pixel electrode layer. When forming a light emitting material over a pixel electrode layer, a mask for selective formation is supported by the spacers, thereby preventing the mask from contacting the pixel electrode layer due to a twist and deflection thereof. Accordingly, such damage as a crack by the mask does not occur in the pixel electrode layer. Thus, the pixel electrode layer does not have a defect in shapes, thereby a display device which performs a high resolution display with high reliability can be manufactured.

A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer.

By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.

A semiconductor device (100) includes: a substrate (11); a first thin film transistor (10A) supported on the substrate (11), the first thin film transistor (10A) having a first active region (13c) which mainly contains a crystalline silicon; and a second thin film transistor (10B) being supported on the substrate (11), the second thin film transistor (10B) having a second active region (17c) which mainly contains an oxide semiconductor having a crystalline portion.