A unit pixel is provided. The unit pixel includes a transparent substrate, a first light blocking layer disposed on the transparent substrate and having windows that transmit light, an adhesive layer covering the first light blocking layer, a plurality of light emitting devices disposed on the adhesive layer to be arranged on the windows, and a second light blocking layer covering side surfaces of the light emitting devices.

This semiconductor light emitting device includes an emission layer, a passivation layer on the emission layer, and a first adhesive layer on the passivation layer. The passivation layer may include a plurality of grooves, and the first adhesive layer may be disposed in each of the plurality of grooves. Arranging the first adhesive layer in the plurality of grooves may enhance fixability. The display device includes a plurality of semiconductor light emitting devices. The semiconductor light emitting devices may include a horizontal semiconductor light emitting device, a flip chip semiconductor light emitting device, or a vertical semiconductor light emitting device.

Disclosed is a Light-Emitting Device-Thin Film Transistor (LED-TFT) integration structure, comprising a substrate comprising a light emitting area and a driving area; a metal reflective film formed on the substrate; a buffer layer formed on the metal reflective film; LED disposed in the light emitting area; a protective layer formed on the LED; a thin film transistor disposed in the driving area and configured to drive the LED; and an ohmic contact metal for electrically connecting a cathode of the LED with the metal reflective film, wherein the LED and the thin film transistor are integrally formed on the substrate.

An emitter includes a light emission region configured to emit light associated with a first optical spectrum, a light emission surface, and an optical element disposed on the light emission surface. A first surface of the optical element, which contacts the light emission surface, is configured to reflect light associated with the first optical spectrum. A second surface of the optical element, opposite the first surface of the optical element, is configured to absorb light associated with a second optical spectrum. At least one aperture is formed in the optical element.

A wiring substrate, a manufacturing method thereof, a light-emitting panel, and a display device are disclosed. The wiring substrate includes: a base substrate (11); and a plurality of metal traces (50) and an organic insulating layer (13), which are located at one side of the base substrate. The metal traces (50) each comprise a first metal layer (141) and a second metal layer (151), which are stacked; the first metal layer (141) is located between the second metal layer (151) and the base substrate (11); an angle between a side wall of the second metal layer (151) and the base substrate (11) is greater than or equal to 90; the area of a contact face between each of the metal traces (50) and the base substrate (11) is greater than or equal to the area of the surface of the second metal layer (151) opposite the first metal layer (141).

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs.

A method of manufacturing a low temperature polycrystalline silicon thin film and a thin film transistor, a thin film transistor, a display panel and a display device are provided. The method includes: forming an amorphous silicon thin film (01) on a substrate (1); forming a pattern of a silicon oxide thin film (02) covering the amorphous silicon thin film (01), a thickness of the silicon oxide thin film (02) located at a preset region being larger than that of the silicon oxide thin film (02) located at other regions; and irradiating the silicon oxide thin film (02) by using excimer laser to allow the amorphous silicon thin film (01) forming an initial polycrystalline silicon thin film (04), the initial polycrystalline silicon thin film (04) located at the preset region being a target low temperature polycrystalline silicon thin film (05). The polycrystalline silicon thin film has more uniform crystal size.

A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.