A photomask according to an exemplary embodiment includes: a mask substrate; and a first test pattern and a second test pattern disposed along a first edge of the mask substrate, wherein the first test pattern has a first outer shape and a first inner shape, the second test pattern has a second outer shape, and the second outer shape of the second test pattern is larger than the first inner shape of the first test pattern and smaller than the first outer shape of the first test pattern.

An array substrate includes a thin film transistor including a drain electrode, a first insulation film included in an upper layer than the drain electrode and including a contact hole overlapping the drain electrode, a pixel electrode included in an upper layer than the first insulation film and overlaps the drain electrode at least inside the contact hole and is connected to the drain electrode, a second insulation film included in an upper layer than the pixel electrode and overlaps the pixel electrode inside the contact hole and extends outside the contact hole, a conductive portion included in an upper layer than the second insulation film and overlaps the pixel electrode at least inside the contact hole, and an insulation portion included in an upper layer than the pixel electrode and in a lower layer than the conductive portion and overlaps the pixel electrode inside the contact hole.

According to some embodiments of the present disclosure, a display device includes an active pattern including a metal oxide, a gate electrode overlapping the active pattern, a first capacitor electrode spaced apart from the active pattern and including a conductive oxide, and a second capacitor electrode on the first capacitor electrode.

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

An array substrate, a manufacturing method of the array substrate, and a display panel are provided. The array substrate includes a photosensitive sensor. The photosensitive sensor includes a photosensitive module and a storage module. The photosensitive module includes a photosensitive semiconductor layer. The storage module includes a first electrode plate and a second electrode plate. Wherein, the photosensitive semiconductor layer is disposed on an extension section of a drain electrode. A number of film layer of the photosensitive sensor is decreased, and photomasks are saved.

An electronic device is provided. The electronic device includes a substrate, a thin-film transistor, a transparent conductive layer, a first organic layer, and a second organic layer. The thin-film transistor is disposed on the substrate and includes a drain electrode. The transparent conductive layer is disposed on the drain electrode and is electrically connected to the drain electrode. The first organic layer is disposed between the drain electrode and the transparent conductive layer. The first organic layer has a through-hole. The second organic layer is disposed in the through-hole. The electronic device has a cell gap. There is a first distance between an upper surface of the first organic layer and an upper surface of the second organic layer. The cell gap and the first distance conform to the following formula: 0<the first distance0.8the cell gap.

The present disclosure provides an array substrate and a manufacturing method for the array substrate. The manufacturing method includes: forming a light-shielding layer, a source, and a drain on the substrate by using a first photomask; forming a semiconductor layer, a gate insulating layer, and a gate which are laminated on the source, the drain, and light-shielding layer by using a second photomask; forming a dielectric layer on the gate and the substrate, and a via hole exposing the drain on the dielectric layer by using a third photomask; and forming a pixel electrode on the dielectric layer by using a fourth photomask.

A drive substrate comprising: a substrate; a first active layer disposed on the substrate; a first insulating layer disposed on the first active layer; a first gate disposed on the first insulating layer; a second insulating layer disposed on the first gate; a second active layer disposed on the second insulating layer; a first electrode and a second electrode disposed on the substrate; a third insulating layer disposed on the first electrode and the second electrode; a third electrode disposed on the third insulating layer.

The array substrate is provided and includes a substrate, a test unit area, first and second flat layers and a terminal area including an input and output terminal areas, the input terminal area includes input terminals for connecting input pins of a driving chip, and the output terminal area includes output terminals for connecting output pins of the driving chip, and each of the input and output terminals includes a second metal layer and a third metal layer disposed on a side of the second metal layer away from the substrate; the second flat layer on a side of the third metal layer away from the substrate and covering edges of the third metal layer; a surface of the first flat layer away from the substrate is not higher than a surface of the second flat layer away from the substrate, in a thickness direction of the substrate.

A display device may include a pixel circuit layer. A first electrode and a second electrode may be on the pixel circuit layer and spaced from each other. A first insulating layer may be on the pixel circuit layer, the first electrode, and the second electrode. A conductive pattern may be on the first insulating layer and electrically insulated from the first electrode and the second electrode. The bank may be on the conductive pattern. Light emitting elements may be located on the first insulating layer between the first electrode and the second electrode, and electrically coupled to the first electrode and the second electrode.