An array substrate includes gate lines extending in a first direction and being portions of a gate metal film, source lines extending in a second direction and being portions of a source metal film, and first and second TFTs arranged alternately in the first direction. The first TFTs include first semiconductor portions that are portions of a first semiconductor film, first gate electrodes that are portions of the gate metal film, and first source electrodes and first drain electrodes that are portions of the source metal film. The second TFTs include second semiconductor portions that are portions of a second semiconductor film above the first semiconductor film via an insulating film, second gate electrodes that are portions of the gate metal film, and second source electrodes and second drain electrodes that are portions of the source metal film. The first and second semiconductor portions are alternately arranged.

In a thin film transistor layer, a first semiconductor film made of an oxide semiconductor, a first gate insulating film made of an inorganic insulating film, a first metal film, a first interlayer insulating film made of an inorganic insulating film, a second metal film, a protective insulating film made of an inorganic insulating film, and a flattening film made of an organic resin material are sequentially layered. The protective insulating film includes a thin film portion provided at a portion where a plurality of first wiring lines formed of the first metal film and a plurality of second wiring lines formed of the second metal film intersect with each other so as to be thinner than a portion of the protective insulating film around the intersecting portion.

A semiconductor device having a high degree of integration is provided. A first and second transistors which are electrically connected to each other and a first insulating layer are included. The first transistor includes a first semiconductor layer, a second insulating layer, and a first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and a fourth to sixth conductive layers. The first insulating layer is positioned over the first conductive layer and includes an opening reaching the first conductive layer. The second conductive layer is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer is positioned over the second insulating layer to overlap with the inner wall of the opening. The third insulating layer is positioned over the fourth conductive layer. The fifth and sixth conductive layers are positioned over the fourth conductive layer with the third insulating layer therebetween. The second semiconductor layer is in contact with top surfaces of the fifth and sixth conductive layers, side surfaces thereof that face each other, and a top surface of the third insulating layer sandwiched between the fifth conductive layer and the sixth conductive layer.

This disclosure provides an array substrate and a preparation method thereof as well as a touch display device. The array substrate includes: a substrate; a plurality of gate lines and a plurality of data lines located on the substrate, wherein the plurality of gate lines extend along a first direction and are arranged in a second direction different from the first direction, the plurality of data lines extend in the second direction and are arranged in the first direction, the plurality of gate lines intersect with the plurality of data lines to define a plurality of pixel areas; and a plurality of touch signal lines located on the substrate, wherein the plurality of touch signal lines extend in the second direction, each of the plurality of touch signal lines comprises a lower touch signal line and an upper touch signal line, and an edge of the upper touch signal line is spaced apart from an edge of the lower touch signal line in the first direction.

An array substrate and a display panel. In the array substrate, orthographic projections of a first scan line connected to a first oxide transistor and a second scan line connected to a second oxide transistor on the substrate are separated from an orthographic projection of a first connection line connected between the first oxide transistor and a first transistor, and an orthographic projection of a second connection line connected between the first oxide transistor and the second oxide transistor on the substrate, thereby solving a problem of lateral crosstalk.

A method for fabricating a single pixel micro LED device for a display panel includes providing a substrate having a pixel driver and fabricating an LED structure layer stacked on top of the substrate. The method further includes bonding the substrate and the LED structure layer together by a bonding layer. The LED structure layer is electrically connected to the pixel driver via the bonding layer. In some embodiments, before bonding the substrate and the LED structure layer, the method includes coating a reflection layer on the LED structure layer. In some embodiments, the method includes patterning the LED structure layer to form a red light LED.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (PLL) circuit or at least one Digital-Lock-Loop (DLL) circuit.

A first insulating layer containing a silicon oxide is disposed on a surface of an insulating member. A transistor is disposed over a part of an area of a first insulating layer. A second insulating layer covers the first insulating layer and the transistor. A first wiring is disposed on the second insulating layer. A through-hole extends through the second insulating layer and the first insulating layer from a lower surface of the first wiring to the insulating member. At least a part of an outer edge of the through-hole overlaps the first wiring in a plan view. The first wiring includes a lower layer that is in contact with the second insulating layer, and the lower layer is formed from Ta, W, a Ta compound, or a W compound.

An electronic device housing may have upper and lower portions that are attached with a hinge. At least one portion of the housing may have a rear planar surface and peripheral sidewalls having edges. A display module may be mounted in the housing. The display module may have glass layers such as a color filter glass layer and a thin-film transistor substrate. The color filter glass layer may serve as the outermost glass layer in the display module. The edges of the display module may be aligned with the edges of the peripheral housing sidewalls to create the appearance of a borderless display for the electronic device. The display module may be provided with an opening that allows a camera or other electronic components to receive light. Traces may be provided on the underside of the thin-film transistor substrate to serve as signal paths for the electrical components.

A lightweight flexible light-emitting device which is able to possess a curved display portion and display a full color image with high resolution and the manufacturing process thereof are disclosed. The light-emitting device comprises: a plastic substrate; an insulating layer with an adhesive interposed therebetween; a thin film transistor over the insulating layer; a protective insulating film over the thin film transistor; a color filter over the protective insulating film; an interlayer insulating film over the color filter; and a white-emissive light-emitting element formed over the interlayer insulating film and being electrically connected to the thin film transistor.