An array substrate includes a substrate, a semiconductor layer over the substrate, a gate over a side of the semiconductor layer away from the substrate, and a source and a drain on sides of the gate. The semiconductor layer includes a channel region, a first doping region, and a first ohmic contact region, which are sequentially connected. A shielding layer is between the substrate and the semiconductor layer. The shielding layer is connected to a fixed potential, and the shielding layer at least partially overlaps with the first doping region in a direction perpendicular to a plane of the substrate.

Provided is an electro-optical device including a transistor, a pixel electrode provided on a light incidence side of the transistor, a lens layer provided in a layer between the transistor and the pixel electrode, and a relay layer serving as a first relay layer that is provided in a layer between the lens layer and the pixel electrode and electrically connected to the pixel electrode, wherein the relay layer includes WSi on the pixel electrode side.

An array substrate and a display device are disclosed. The array substrate includes a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a pixel electrode arranged in a region defined by an adjacent gate line and an adjacent data line, and a thin film transistor arranged at an intersection of the gate lines and the data lines. A drain of the thin film transistor is connected with the pixel electrode through a via hole. The gate lines further include a widening portion between adjacent data lines. The widening portion comprises a recess structure. An orthogonal projection of the recess structure on the base substrate at least partly overlaps that of the drain of the thin film transistor on the base substrate.

A display apparatus includes a substrate, a gate electrode overlapping the substrate, and a semiconductor layer positioned between the substrate and the gate electrode. The semiconductor layer includes a first layer and a second layer positioned between the first layer and the gate electrode. A hydrogen content of the first layer is greater than a hydrogen content of the second layer.

The present disclosure relates to a pixel arrangement structure, a display panel and a display device. The pixel arrangement structure includes: a first pixel area including a plurality of first-category pixel groups, each of which is arranged according to a first arrangement manner; and a second pixel area including a plurality of second-category pixel groups, each of which is arranged according to a second arrangement manner; wherein the first pixel area is adjacent to the second pixel area, and the first pixel area has a pixel density lower than a pixel density of the second pixel area. Embodiments of the present disclosure can improve the optical signal reception of the under-screen functional elements.

Provided is an array substrate. The array substrate includes a display region and a non-display region located at a periphery of the display region, wherein the array substrate includes a substrate; a first transistor and a second transistor that are disposed on the substrate, wherein the first transistor is disposed in the display region, and the second transistor is disposed in the non-display region; and a data line and a pixel electrode that are disposed in the display region, wherein the data line is disposed on a side of the first active layer close to the substrate and is lapped with the first active layer, and the pixel electrode is disposed on a side of the first gate facing away from the substrate and is lapped with the first active layer.

The present application relates to the technical field of display panels, and provides an array substrate and a method for preparing the same, and a display panel. The array substrate includes a base substrate, a buffer layer, an active layer, a gate insulation layer, a first gate, an interlayer insulation layer, a source and a drain that are laminated. The active layer includes the first active layer and the two second active layers, and the first active layer forms the channel region.

According to one embodiment, a display device includes first semiconductor layers crossing a first scanning line in a non-display area, the first semiconductor layers being a in number, second semiconductor layers crossing a second scanning line in the non-display area, the second semiconductor layers being b in number, and an insulating film disposed between the first and second semiconductor layers and the first and second scanning lines, wherein a and b are integers greater than or equal to 2, and a is different from b, and the first and second semiconductor layers are both entirely covered with the insulating film.

A display device includes: a substrate; and a semiconductor layer disposed on the substrate, and including a first area, a second area, and a third area that are sequentially positioned by dividing the semiconductor layer into three areas in a thickness direction of the semiconductor layer, wherein the semiconductor layer includes polycrystalline silicon, a concentration of fluorine contained in the semiconductor layer has a first peak value in the first area and a second peak value in the third area, and the first peak value of the concentration of the fluorine in the semiconductor layer is about 30% or less of the second peak value of the concentration of the fluorine in the semiconductor layer.

A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.