Drive substrates and display panels are provided. In a thin film transistor of the drive substrate, a structure with double-gate and double-active layer is formed by a first active layer, a first gate, a first sub-gate of a second gate, and a part of a second active layer in an area adjacent to an output electrode; and a structure with single active layer and top gate is formed by a second sub-gate of the second gate and a part of the second active layer in an area adjacent to an input electrode. The first gate and the second gate together control a first channel of the first active layer and a first portion of a second channel of the second active layer.

Disclosed are an array substrate and a display panel. The array substrate includes a substrate and a first transistor disposed on the substrate. The first transistor includes a first active layer disposed on the substrate, a first channel portion, a first doped portion, a second doped portion, a first gate disposed on one side of the first active layer, a source and a drain. The first doped portion and the second doped portion are connected to opposite ends of the first channel portion, respectively. The first doped portion includes a first doped sub-portion and a second doped sub-portion connected between the first channel portion and the first doped sub-portion. A doping concentration of ions in the second doped sub-portion is less than that in the first doped sub-portion, and a doping concentration of ions in the first doped sub-portion is the same as that in the second doped portion.

A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.

A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.

An electronic element includes a substrate, and a vertical-support-element located on the substrate, the vertical-support-element extending away from the substrate and having a perimeter over the substrate, wherein the vertical-support-element has a reentrant profile around at least a portion of the perimeter. Three or more vertical transistors are positioned around the perimeter of the vertical-support-element, each of the transistors having a semiconductor channel being located in a corresponding region of the reentrant profile.

A semiconductor device includes a first transistor including a first electrode, a first insulating layer above the first electrode, the first insulating layer having a first side wall, a first oxide semiconductor layer on the first side wall, the first oxide semiconductor layer being connected with the first electrode, a first gate electrode, a first gate insulating layer, and a second electrode above the first insulating layer, the second electrode being connected with the first oxide semiconductor layer; and a second transistor including a third electrode, a fourth electrode separated from the third electrode, a second oxide semiconductor layer between the third electrode and the fourth electrode, the second oxide semiconductor layer being connected with each of the third electrode and the fourth electrode, a second gate electrode, and a second gate insulating layer.

A semiconductor device including an oxide semiconductor in which on-state current is high is provided. The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. Furthermore, the first transistor and the second transistor are transistors having a top-gate structure. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode. The regions of the oxide semiconductor film which contain the impurity element function as low-resistance regions. Furthermore, the regions of the oxide semiconductor film which contain the impurity element are in contact with a film containing hydrogen. The first transistor provided in the driver circuit portion includes two gate electrodes between which the oxide semiconductor film is provided.

A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased. As a consequence, each such line is formed so as to be thicker than could otherwise be achieving without causing defects in the rubbing process of an alignment layer. Additionally, no widening of these lines is needed, thus preserving the aspect ratio of the device. The gate insulating and semiconducting layers that in part make up the thin film transistors that help control the operation of the pixels of the device may also be designed to take into account the increased thickness of the lines.

A display device includes a pixel circuit disposed on a substrate, and a display element on the pixel circuit. The pixel circuit includes a first thin-film transistor comprising a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, a second thin-film transistor comprising a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer being connected to the first semiconductor layer and the first gate electrode, a first shielding layer overlapping the second semiconductor layer, and a second shielding layer overlapping the second semiconductor layer and stacked on the first shielding layer.