A semiconductor device having a high degree of integration is provided. A first and second transistors which are electrically connected to each other and a first insulating layer are included. The first transistor includes a first semiconductor layer, a second insulating layer, and a first to third conductive layers. The second transistor includes a second semiconductor layer, a third insulating layer, and a fourth to sixth conductive layers. The first insulating layer is positioned over the first conductive layer and includes an opening reaching the first conductive layer. The second conductive layer is positioned over the first insulating layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, an inner wall of the opening, and the second conductive layer. The third conductive layer is positioned over the second insulating layer to overlap with the inner wall of the opening. The third insulating layer is positioned over the fourth conductive layer. The fifth and sixth conductive layers are positioned over the fourth conductive layer with the third insulating layer therebetween. The second semiconductor layer is in contact with top surfaces of the fifth and sixth conductive layers, side surfaces thereof that face each other, and a top surface of the third insulating layer sandwiched between the fifth conductive layer and the sixth conductive layer.

Drive substrates and display panels are provided. In a thin film transistor of the drive substrate, a structure with double-gate and double-active layer is formed by a first active layer, a first gate, a first sub-gate of a second gate, and a part of a second active layer in an area adjacent to an output electrode; and a structure with single active layer and top gate is formed by a second sub-gate of the second gate and a part of the second active layer in an area adjacent to an input electrode. The first gate and the second gate together control a first channel of the first active layer and a first portion of a second channel of the second active layer.

As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

An embodiment of the application discloses a panel and a manufacturing method thereof. In the panel, a thin-film transistor layer, a first conductive layer, a light-emitting diode (LED), and a second conductive layer are sequentially disposed on a substrate. The LED includes a first end and a second end. The first end is disposed on the first electrode. The second end is disposed on the second electrode. The second conductive layer includes a first conductive portion and a second conductive portion. The first conductive portion is electrically connected to the first end and the first electrode. The second conductive portion is electrically connected to the second end and the second electrode.

Provided are a display panel and a display device. The display panel includes a base substrate; a first transistor, a second transistor and a third transistor, where the first transistor, the second transistor and the third transistor are formed on the base substrate, the first transistor includes a first active layer, a first gate, a first source, and a first drain, the first active layer contains silicon, the second transistor includes a second active layer, a second gate, a second source, and a second drain, and the second active layer contains an oxide semiconductor; and a first insulating layer and a second insulating layer, where the first insulating layer is disposed on one side of the second active layer facing away from the base substrate and between the second gate and the second active layer.

It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

A display device includes a substrate, an active pattern disposed on the substrate, a gate electrode overlapping the active pattern, an inorganic insulation layer covering the active pattern, a source metal pattern and an etch-delaying pattern. The source metal pattern includes a first portion that is disposed on the inorganic insulation layer, and a second portion that passes through the inorganic insulation layer and electrically contacts the active pattern. The etch-delaying pattern is disposed between the active pattern and the first portion of the source metal pattern, contacts the second portion of the source metal pattern, and includes a different material from the inorganic insulation layer.

A polishing slurry is disclosed which includes about 0.01 wt % to about 10 wt % of polishing particles, about 0.005 wt % to about 0.1 wt % of a dispersing agent, about 0.001 wt % to about 1 wt % of an oxide-polishing promoter including a pyridine compound, about 0.05 wt % to about 0.1 wt % of a nitride-polishing inhibitor including an amino acid or an anionic organic acid, and water. A method for manufacturing a display device including an active pattern disposed on a base substrate, a gate metal pattern including a gate electrode overlapping the active pattern, a planarized insulation layer disposed on the gate metal pattern, and a source metal pattern disposed on the planarized insulation layer is also disclosed.

Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.

A thin film transistor array substrate and a display device are provided. The thin film transistor array substrate includes a first semiconductor layer, a second semiconductor layer, a first gate electrode, a conductive layer, a second gate electrode, a third gate electrode, and an intermediate insulating layer. The first semiconductor layer and the second semiconductor layer are made of different semiconductor materials. The first gate electrode and the conductive layer overlap with the first semiconductor layer. The second gate electrode and the third gate electrode overlap with the second semiconductor layer. The intermediate insulating layer is disposed between the second semiconductor layer and the second gate electrode.