A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 m or less.

A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 m or less.

A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure.

A semiconductor device according to an embodiment includes: a semiconductor part including a first main surface and a second main surface on an opposite side of the first main surface; a surface structure part provided on the first main surface, the surface structure part including a first electrode; a second electrode provided on the second main surface; a first protective resin film configured to cover an upper surface of the surface structure part; and a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part.

A processing method for processing a single-crystal silicon wafer that has a first surface and a second surface formed in such a manner that a specific crystal plane included in a crystal plane {100} is exposed in each of the first and second surfaces and has devices formed in the respective regions marked out by planned dividing lines in the first surface. The method includes forming dividing origins along each planned dividing line, forming a separation layer along the crystal plane of the second surface through relatively moving a focal point and the wafer along a first direction that is parallel to the crystal plane of the second surface and in which an acute angle formed between the first direction and the crystal orientation <100> is equal to or smaller than 5, and separating the wafer into a first-surface-side wafer including devices and a second-surface-side wafer including no devices.

A dicing die-bonding film including a die-bonding film and a dicing film having a pressure-sensitive adhesive layer laminated on the die-bonding film. The thickness of the die-bonding film is 10 m or less. The thickness of the pressure-sensitive adhesive layer is less than 10 m. The dicing film may further have a base material film, and the pressure-sensitive adhesive layer may be provided on the base material film.

A method of manufacturing a semiconductor device includes forming a light blocking film configured to block first light within a first wavelength band on an edge region of an upper surface of a light-transmitting carrier substrate; forming a photosensitive adhesive layer on the upper surface of the light-transmitting carrier substrate to at least partially cover the light blocking film; bonding a product substrate to the upper surface of the light-transmitting carrier substrate using the photosensitive adhesive layer; partially curing the photosensitive adhesive layer by irradiating the light through the light-transmitting carrier substrate, wherein a portion of the photosensitive adhesive layer overlapping the light blocking film is not cured; processing the product substrate to form a plurality of semiconductor devices after the partially curing of the photosensitive adhesive layer; and cutting the product substrate such that the plurality of semiconductor devices are cut into a plurality of separate individual semiconductor devices.

A manufacturing method of chips includes forming modified layers that become points of origin of dividing along planned dividing lines, grinding the back surface of the wafer by grinding abrasive stones to thin the wafer into a finished thickness, and dividing the wafer into the chips along the planned dividing lines using the modified layers as the points of origin. The manufacturing method also includes sticking an expanding tape having elasticity to the back surface of the wafer for which grinding processing has been executed, expanding the expanding tape and widening the interval between the respective chips along the planned dividing lines.

An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material. Embodiments include methods of fabricating the integrated passive dies.