A combination structure of semiconductor deep trench devices includes: a deep trench insulator device, which includes at least one deep trench ring unit, wherein the deep trench ring unit includes: a deep trench ring, a first dielectric side wall layer and a first poly silicon fill region; and a deep trench capacitor device, which includes a plurality of deep trench capacitor units and a cathode, wherein each of the deep trench capacitor units includes: a deep trench hole; a second dielectric side wall layer; and a second poly silicon fill region. The deep trench hole is formed by etching a semiconductor substrate with a same etch process step with the deep trench ring. The first dielectric side wall layer and the second dielectric side wall layer is formed by a same oxide growth process step.

A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

A radio frequency device includes an optically transparent, electrically insulating substrate; a plurality of optically transparent, electrically conductive cells disposed on the substrate; a thin film transistor electrically coupled between an optically transparent electrode of a first one of the cells and an optically transparent electrode of a second one of the cells; and an optically transparent conductive control trace electrically coupled to a control terminal of the transistor. In an example, at least one of the cells is a transparent conductive oxide thin film. Electrodes of the transistor may also be optically transparent.

Techniques are described for designing and forming cells comprising transistor devices for an integrated circuit. In an example, an integrated circuit structure includes a plurality of cells arranged in rows where some rows have different cell heights compared to other rows. Additionally, the various rows of cells may contain semiconductor nanoribbons having different widths between different rows. For example, any number of first rows of cells can each have a first height and any number of second rows can each have a second height that is smaller than the first height. The first rows of cells may include transistors with semiconductor nanoribbons having a first width and the second rows of cells may include transistors with semiconductor nanoribbons having a second width smaller than the first width. In some cases, any of the first rows of cells may also include transistors with semiconductor nanoribbons having the second width.

Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.

A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (PLL) circuit or at least one Digital-Lock-Loop (DLL) circuit.

Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.

A physically unclonable function (PUF) cell array includes a first PUF cell in a first column in a first direction, a second PUF cell in a second column, and a first power rail. The first PUF cell includes a first set of conductive structures that include a first conductive structure extending in the second direction and a second conductive structure extending in the first direction. The second PUF cell includes a second set of conductive structures that include a third conductive structure extending in the second direction and a fourth conductive structure extending in the first direction. The first power rail overlapping a first boundary of the first and second PUF cell. At least the first and third conductive structure, or the second and the fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell.