The present disclosure generally relates to integrated devices with a conductive barrier structure. In an example, a semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a gate, and a conductive structure. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer. The conductive structure is electrically coupled between the conductive barrier structure, the channel layer, and the barrier layer.

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.

A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level, The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

A 3D integrated circuit device, including: a first layer including first transistors, overlaid by a second layer including second transistors, overlaid by a third layer including third transistors, where the first layer, the second layer and the third layer are each thinner than 2 microns, where the first layer includes first circuits including at least one of the first transistors, where the second layer includes second circuits including at least one of the second transistors, and where the third layer includes a charge pump circuit and control circuits to control the first circuits and the second circuits

An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either a body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If a body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel transistor formed in an isolated P-well and an N-channel transistor coupled in series with the P-channel transistor. Forming the P-channel transistor in the isolated P-well essentially eliminates a raised threshold voltage due to body effect.

A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region.