A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

An electrostatic discharge (ESD) protection cell region (of a semiconductor device) includes a resistor-diode ladder and a power clamp circuit coupled in parallel between a first power rail PR1 and a second power rail PR2. The resistor-diode ladder is also coupled between an input/output (I/O) pad of the semiconductor device and core circuitry of the semiconductor device. The resistor-diode ladder includes: a first diode coupled between a first node and the first power rail; a first resistor coupled between the first node and a second node; a second diode coupled between the second node and the first power rail; a third diode coupled between the first node and the second power rail; and a fourth diode coupled between the second node and the second power rail. The first node is coupled to the I/O pad. The resistor-diode ladder is coupled between the I/O pad and the core circuitry.

An integrated circuit includes a first semiconductor device with an N type region biased by a first terminal and a second semiconductor device with a second region. An N type guard region is located laterally between the N type region of the first semiconductor device and the second region. A P type region is isolated in the N type guard region and is biased by a second terminal. The N type guard region is either electrically coupled to the second terminal through a resistor circuit or is characterized as floating.

Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.

An electronic device is provided, which comprises: a substrate comprising an active region and a peripheral region; a common conductive line disposed corresponding to the peripheral region of the substrate; and a scan line disposed on the substrate, wherein the scan line is electrically connected to a first static discharge conductive line through a first electrostatic protection circuit in the peripheral region, wherein the common conductive line is electrically separated from the first static discharge conductive line; wherein in a top view of the substrate, there is a first distance between the common conductive line and the first static discharge conductive line, and the first distance is greater than or equal to 1.5 m and less than or equal to 12 mm.

Provided is an image sensor circuit, including a pixel array and a plurality of different control circuits. The pixel array comprises a plurality of pixel circuit groups arranged in an array. Each pixel circuit group comprises a plurality of pixel circuits that generate corresponding sensitivity values over exposure duration. The pixel circuits include a first quantity of first pixel circuits, and a second quantity of second pixel circuits. The plurality of different control circuits are respectively coupled to different pixel circuits to control the exposure duration thereof with different transmission signals. The different control circuits are also set to control different pixel circuits to output photo-sensed values at different frame rates. The image sensor circuit periodically generates the pixel value of each pixel circuit group according to first and second exposure durations, first and second frame rates, and first and second light sensitivity values of each pixel circuit group.

A transient voltage suppressor (TVS) device includes a silicon controlled rectifier (SCR) as the clamp device between a high-side steering diode and a low-side steering diode. The SCR includes alternating emitter and base regions arranged interleaving in a direction along a major surface of a semiconductor layer and orthogonal to a current path of the SCR. The TVS device realizes low capacitance and high holding voltage at the protected node.

An I/O circuit is formed by combining plural types of standard cells contained in a cell library. For example, the standard cell includes a first element forming region having, formed therein, protection target elements each having a gate electrically connected to an external terminal, a second element forming region arranged in immediate proximity to the external terminal and having first protection elements formed therein, and a third element forming region arranged between the first and second element forming regions and having transistors formed therein. The transistors each have a drain connected to gates of the protection target elements and a source, gate, and back gate all connected to a power supply or ground terminal, thus functioning as a second protection element.

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.