A semiconductor electrostatic discharge (ESD) protection circuit comprises an N diode for limiting negative going voltages with reference to ground (V.sub.SS) and a P diode for limiting positive going voltages with reference to a positive supply voltage (V.sub.DD). The N-diode is formed in a single P-well surrounded by an N-well ring. The P-diode is formed in a single N-well surrounded by a P-well ring. The N-diode comprises a plurality of N+ fingers, each N+ finger is surrounded by a P+ guard ring. The P-diode comprises a plurality of P+ fingers, each P+ finger surrounded by an N+ guard ring. The plurality of N+ fingers and P+ fingers are coupled to an input-output pad. The P+ guard rings are coupled to ground (V.sub.SS) and the N+ guard rings are coupled to the positive supply voltage (V.sub.DD).

An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. A resistive element is coupled between the conductive contact and first circuitry. Second circuitry is coupled between the resistive element and the conductive contact. The second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. The resistive element is disposed in a first metallization layer of the IC device. A first dielectric layer is adjacent to the first metallization layer. A second metallization layer is adjacent to the first dielectric layer. A height of the first dielectric layer and the second metallization layer is a first distance. A zone overlaps the resistive element, and extends a second distance away from the resistive element. The zone is free of conductive material and the second distance is greater than the first distance.

A semiconductor device includes a first metal-oxide semiconductor (MOS) transistor on a substrate, a pickup region adjacent to one side of the first MOS transistor, and a protection diode adjacent to another side of the first MOS transistor. Preferably, the first MOS transistor includes a first gate structure on the substrate and a first source/drain region adjacent to two sides of the first gate structure, the protection diode is electrically connected to the first gate structure, and the pickup region and the protection diode include different conductive type.

A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprising a body ring structure, forming a source and a body region in the epitaxial layer, forming an interlayer dielectric layer over the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure in the interlayer dielectric layer, forming a source contact connected to the source, and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact underneath the substrate.

A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.

An integrated circuit includes a first horizontal conductor and a second horizontal conductor. The integrated circuit includes a first diode between a first first-type block and a first second-type block, a second diode between a second first-type block and a second second-type block, and a third diode between a third first-type block and a third second-type block. The first first-type block and the first second-type block are aligned along a first column. The second first-type block and the second second-type block are aligned along a second column. The third first-type block and the third second-type block are aligned along a third column. The second first-type block is connected to the first second-type block through the second horizontal conductor. The third first-type block is conductively connected to the second second-type block through the first horizontal conductor.

A package structure is provided. The package structure includes a leadframe, a GaN power device, and an electrostatic discharge protection component. The leadframe includes a gate pad, a source pad, and a drain pad, which are disposed on the leadframe. The GaN power device has a gate end. The GaN power device is disposed on the source pad of the leadframe. The electrostatic discharge protection component includes a first pad. The first pad is disposed on the electrostatic discharge protection component. The electrostatic discharge protection component is disposed on the source pad of the leadframe. The gate end of the GaN power device is electrically connected to the first pad of the electrostatic discharge protection component. The first pad of the electrostatic discharge protection component is electrically connected to the gate pad of the leadframe.

An embodiment relates to a n-type planar gate DMOSFET comprising a Silicon Carbide (SiC) substrate. The SiC substrate includes a N+ substrate, a N drift layer, a P-well region and a first N+ source region within each P-well region. A second N+ source region is formed between the P-well region and a source metal via a silicide layer. During third quadrant operation of the DMOSFET, the second N+ source region starts depleting when a source terminal is positively biased with respect to a drain terminal. The second N+ source region impacts turn-on voltage of body diode regions of the DMOSFET by establishing short-circuitry between the P-well region and the source metal when the second N+ source region is completely depleted.

A semiconductor device is provided. The semiconductor device includes an input/output cell, a core logic circuit, a first power supply cell, a second power supply cell, a third power supply cell and a fourth power supply cell. Each of the power supply cells includes a protection circuit and a bidirectional diode.

A semiconductor device includes a first well region, a second well region, a body region, and a cathode region. The impurity concentration of the body region is higher than the impurity concentration of the first well region, and the impurity concentration of the second well region is higher than the impurity concentration of the body region. In plan view, the body region includes the cathode region, and the cathode region includes the second well region. The cathode region configures a cathode of a Zener diode, and the first well region, the second well region, and the body region configure an anode of the Zener diode.