An electrostatic discharge circuit includes two or more GGNMOS transistors where each transistor includes two types of body contact regions. Body contact regions of one type are non substrate isolated from body contact regions of the other type. A body contact region of one type is electrically coupled to the source region of its transistor and a body contact region of the other type is electrically connected to at least one other body contact region of the same type of another GGNMOS transistor.

The present disclosure relates to semiconductor devices. An example semiconductor device includes a first well region and a second well region isolated from each other by a first device isolation film; an NPN transistor provided by a first collector region formed in the first well region and including first conductivity-type impurities, and a first emitter region formed in the second well region and including the first conductivity-type impurities; a PNP transistor provided by a second emitter region formed in the first well region and including second conductivity-type impurities different from the first conductivity-type, and a second collector region formed in the second well region and including the second conductivity-type impurities; and an NMOS transistor including a source region and a drain region formed in the second well region and including the first conductivity-type impurities, and a gate structure disposed between the source region and the drain region.

An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including a well, a field-effect transistor including a gate, a source having a doped region in the well, and a drain, and a silicon-controlled rectifier including a doped region in the well.

A transient voltage suppressor (TVS) device includes a silicon controlled rectifier (SCR) as the clamp device between a high-side steering diode and a low-side steering diode. The SCR includes alternating emitter and base regions arranged interleaving in a direction along a major surface of a semiconductor layer and orthogonal to a current path of the SCR. The TVS device realizes low capacitance and high holding voltage at the protected node.

An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.

A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.

An electro-static discharge (ESD) protection device includes a first PN diode, a second PN diode and a silicon controlled rectifier (SCR). The first PN diode and the second PN diode are coupled in series between a pad and a ground voltage to provide a first discharge current path. The SCR is coupled between the pad and the ground voltage to provide a second discharge current path. The SCR has a PNPN structure.

An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.