An integrated circuit (IC) device comprises a conductive contact at a surface of the IC device. A resistive element is coupled between the conductive contact and first circuitry. Second circuitry is coupled between the resistive element and the conductive contact. The second circuitry is further coupled with a supply line and comprises at least one of a diode or a power clamp. The resistive element is disposed in a first metallization layer of the IC device. A first dielectric layer is adjacent to the first metallization layer. A second metallization layer is adjacent to the first dielectric layer. A height of the first dielectric layer and the second metallization layer is a first distance. A zone overlaps the resistive element, and extends a second distance away from the resistive element. The zone is free of conductive material and the second distance is greater than the first distance.

Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

A semiconductor device that includes an n-buried layer, a p-well region over the n-buried layer, an n-channel MOSFET that includes an n-drain region, and a vertical NPN BJT having a collector that is the n-drain region and a base that is the p-well region. The p-well region is floating.

A power semiconductor device includes: a semiconductor body with a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body; a second load terminal at a second side of the semiconductor body opposite the first side, the power semiconductor device configured to conduct a load current between the load terminals; a control terminal at the first side configured to receive a control signal for controlling the load current; within an active region at least partially surrounded by an edge termination region, first trenches laterally confining mesas for conducting the load current, having control trenches electrically connected to the control terminal, and arranged in accordance with a first average pitch; and in a region laterally overlapping the control terminal, second trenches arranged in accordance with a second average pitch different from the first average pitch and electrically connected to the control terminal.

A semiconductor device is provided. The semiconductor device includes an input/output cell, a core logic circuit, a first power supply cell, a second power supply cell, a third power supply cell and a fourth power supply cell. Each of the power supply cells includes a protection circuit and a bidirectional diode.

A semiconductor device with ESD protection structure and a method of making it are disclosed. The semiconductor device with ESD protection structure includes at least one gate and source and drain regions on opposite sides of the at least one gate that constitute at least a discharging MOSFET. The gate includes first gate portions having a first dopant concentration and a second gate portion having a second dopant concentration. The first dopant concentration is lower than the second dopant concentration. The at least one first gate portions are lower portions of the gate above the edges of an active area, and the second gate portion is the remaining portion of the at least one gate other than the first gate portions.

The present disclosure relates to semiconductor devices. An example semiconductor device includes a first well region and a second well region isolated from each other by a first device isolation film; an NPN transistor provided by a first collector region formed in the first well region and including first conductivity-type impurities, and a first emitter region formed in the second well region and including the first conductivity-type impurities; a PNP transistor provided by a second emitter region formed in the first well region and including second conductivity-type impurities different from the first conductivity-type, and a second collector region formed in the second well region and including the second conductivity-type impurities; and an NMOS transistor including a source region and a drain region formed in the second well region and including the first conductivity-type impurities, and a gate structure disposed between the source region and the drain region.

A semiconductor structure is provided in the present invention, including a substrate, a deep N-well formed in the substrate, a first well formed in the deep N-well, a first gate formed on the first well, a first source and a first drain formed respectively at two sides of the first gate in the first well, a first doped region formed in the first well, and a metal interconnect electrically connected with the first source and the first doped region, wherein an area of the deep N-well multiplied by a first parameter is a first factor, an area of the first gate multiplied by a second parameter is a second factor, and an area of the metal interconnect divided by a sum of the first factor and the second factor is less than a specification value.