A device is disclosed that includes a first transistor, a second transistor, and a first PODE device. The second transistor is electrically coupled to the first transistor. The first PODE device is adjacent to a drain/source region of the second transistor. A control end of the first PODE device is electrically coupled to a drain/source end of the second transistor.

A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.

The electrostatic protective device includes an insulator and a semiconductor layer. The semiconductor layer includes a device forming region and a device separating region. The device forming region includes a primary first conductive impurity diffused layer, a body region, a secondary first conductive impurity diffused layer, and a second conductive region that are arranged in order. The second conductive region includes a second conductive impurity diffused layer separated electrically from the body region. The device separating region includes a device separating layer that surrounds the device forming region. A gate electrode is further provided on the body region in the semiconductor layer with an insulating film interposed in between.

A semiconductor unit includes: a transistor configured to provide electrical conduction between a first terminal and a second terminal, based on a trigger signal; and a trigger device formed in a transistor region where the transistor is formed, and configured to generate the trigger signal, based on a voltage applied to the first terminal.

A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

Disclosed is an electro-static discharge (ESD) protection unit, an array substrate, a display panel and a display device. The electro-static discharge protection unit comprises n stages of thin film transistors connected in series, wherein n2, a control electrode of each stage of thin film transistor is floating, a source electrode of a first stage of thin film transistor is connected with an electro-static generation terminal, a drain electrode of each of the first to .sup.n1th stages of thin film transistors is connected with a source electrode of a next stage of thin film transistor, respectively, and a drain electrode of a .sup.nth stage of thin film transistor is connected with an electro-static discharge terminal; or wherein n3, a control electrode of each stage of thin film transistor is floating, a source electrode of a first stage of thin film transistor is connected with a first electro-static generation terminal, a drain electrode of each of the first to .sup.n1th stages of thin film transistors is connected with a source electrode of a next stage of thin film transistor, respectively, and a drain electrode of a .sup.nth stage of thin film transistor is connected with a second electro-static generation terminal. The ESD protection unit can still protect signals in an electro-static generation terminal from being interfered when the thin film transistor adjacent to the electro-static generation terminal is broken down due to ESD, thereby avoiding failure due to ESD.