An integrated circuit is provided and includes a first active region of a first conductivity type coupled to a first voltage terminal and corresponding to a first terminal of a first transistor and a first terminal of a second transistor included in an inverter of a level shifter circuit, wherein the first transistor is configured to discharge electrostatic charges to the first voltage terminal; and second and third active regions, corresponding to a third transistor, of a second conductivity type different from the first conductivity type, wherein the second active region is coupled to a second voltage terminal, and the third active region is coupled to a first terminal, different from the second voltage terminal, of the level shifter circuit. The third transistor is configured to transmit a first supply voltage from the second voltage terminal for the integrated circuit.

A semiconductor device includes: first switching elements arranged in a first direction and each including a first gate wire extending in a second direction; and a back gate guard ring surrounding the first switching elements. The first switching elements are connected to each other in parallel and connected between a first pad and a second pad. The first switching elements include a driver switching element, the driver switching element being at least one first switching element located between two first end switching elements located at opposite ends of the first switching elements in the first direction. The first switching elements excluding the driver switching element include a first protection switching element, the first gate wire of the first protection switching element being connected to the first pad or the second pad.

A semiconductor device, such as a fin field-effect transistor (FinFET), that can provide advantages in terms of electrostatic discharge protection. The semiconductor device includes a fin with an undoped region, a first doped region, a second doped region, and a third doped region positioned between the first doped region and the second doped region. The semiconductor device further includes a gate disposed on the undoped region of the fin, a silicide layer disposed on the third doped region, and an interconnect disposed on the silicide layer to form a drain.

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.

A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.

A semiconductor device including a first line configured to receive a power supply voltage, a second line configured to be coupled to a load of the semiconductor device, first and second metal-oxide-semiconductor (MOS) transistors coupled in series between the first line and the second line, each of the first and second MOS transistors having a drain electrode and a gate electrode, the drain electrode of the first MOS transistor being coupled to the drain electrode of the second MOS transistor, a third line coupled to the gate electrode of the first MOS transistor, and a fourth line coupled to the gate electrode of the second MOS transistor, the third and fourth lines being electrically separated from each other.

A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.

An electrostatic discharge (ESD) protection device includes a first trigger element and a first silicon control rectifier (SCR) element. The first trigger element has a first parasitic bipolar junction transistor (BJT) formed in a substrate. The first SCR element has a second parasitic BJT formed in the substrate. The first parasitic BJT and the second parasitic BJT has a common parasitic bipolar base, and the first parasitic BJT has a trigger voltage substantially lower than that of the second parasitic BJT.