The invention provides methods of making immune effector cells (e.g., T cells, NK cells) that can be engineered to express a chimeric antigen receptor (CAR), compositions and reaction mixtures comprising the same, and methods of treatment using the same.

An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

An electrostatic protection circuit and a semiconductor device include: a first diode whose anode is connected to a signal terminal; a second diode whose cathode is connected to a cathode of the first diode and whose anode is connected to a GND terminal; and a depletion type MOS transistor connected in parallel with the first diode.

Provided is a wide bandgap semiconductor device having a configuration capable of detecting a temperature of a substrate with high accuracy during operation of a main transistor. The wide bandgap semiconductor device includes: a substrate mainly including a wide bandgap semiconductor; a vertical MOSFET serving as a main transistor provided in a first region of the substrate; and a lateral MOSFET for temperature detection provided in a second region of the substrate.

A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.

A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.

A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first and second node, a discharging circuit coupled between the first and second node, a charging circuit, and a first conductive structure on the back-side of the semiconductor wafer, and extending into the first well and being directly coupled to the first source of the first transistor. The discharging circuit includes a first transistor of a first type in a semiconductor wafer. The first transistor includes a first well, a first gate coupled to the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. a charging circuit coupled to the second node and the third node, and configured to charge the third node during an ESD event at the second node.