H10F10/144

MULTIJUNCTION SOLAR CELL
20240405145 · 2024-12-05 ·

A multijunction solar cell including an upper first solar subcell having an emitter and base layers forming a photoelectric junction; a second solar subcell disposed under and adjacent to the upper first solar subcell, and having an emitter and base layers forming a photoelectric junction; and a third solar subcell disposed under and adjacent to the second solar subcell and having an emitter and base layers forming a photoelectric junction; wherein at least one of the base and emitter layers of at least a particular solar subcell from among the upper first solar subcell, the second solar subcell, and the third solar subcell has a graded band gap throughout at least a portion of thickness of its active layer adjacent to the photoelectric junction and being in a range of 20 to 300 MeV less than a band gap in the active layer in both the emitter layer and the base layer spaced away from the photoelectric junction.

Tandem nanofilm photovoltaic cells joined by wafer bonding

An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 m to about 10 m. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means.

Scalable voltage source

A scalable voltage source having a number N of partial voltage sources implemented as semiconductor diodes connected to one another in series, wherein each of the partial voltage sources has a semiconductor diode with a p-n junction. A tunnel diode is formed between sequential pairs of partial voltage sources, wherein the tunnel diode has multiple semiconductor layers with a larger band gap than the band gap of the p/n absorption layers and the semiconductor layers with the larger band gap are each made of a material with modified stoichiometry and/or a different elemental composition than the p/n absorption layers of the semiconductor diode. The partial voltage sources and the tunnel diodes are monolithically integrated together, and jointly form a first stack with a top and a bottom, and the number N of partial voltage sources is greater than or equal to two.

Highly doped layer for tunnel junctions in solar cells
09722131 · 2017-08-01 · ·

A highly doped layer for interconnecting tunnel junctions in multijunction solar cells is presented. The highly doped layer is a delta doped layer in one or both layers of a tunnel diode junction used to connect two or more p-on-n or n-on-p solar cells in a multijunction solar cell. A delta doped layer is made by interrupting the epitaxial growth of one of the layers of the tunnel diode, depositing a delta dopant at a concentration substantially greater than the concentration used in growing the layer of the tunnel diode, and then continuing to epitaxially grow the remaining tunnel diode.

COMPOUND PHOTOVOLTAIC CELL
20170213932 · 2017-07-27 · ·

A compound photovoltaic cell includes a substrate, a first cell made of a first semiconductor material and formed on the substrate, a tunnel layer, and a second cell made of a second semiconductor material lattice mismatched with a material of the substrate, connected to the first cell via the tunnel layer, and disposed on an incident side with respect to the first cell, wherein band gaps of the first and the second cells become smaller from an incident side to a back side, and wherein the tunnel layer includes a p-type layer disposed on the incident side and a n-type layer disposed on the back side, the p-type layer being a p.sup.+-type (Al)GaInAs layer, the n-type layer being an n.sup.+-type InP layer, an n.sup.+-type GaInP layer having a tensile strain with respect to InP or n.sup.+-type Ga(In)PSb layer having a tensile strain with respect to InP.

Structures for Increased Current Generation and Collection in Solar Cells with Low Absorptance and/or Low Diffusion Length

The present disclosure generally relates to a solar cell device that a first Bragg reflector disposed below a first solar cell and a second Bragg reflector disposed below the first Bragg reflector, wherein the first solar cell comprises a dilute nitride composition and has a first bandgap, wherein the first Bragg reflector is operable to reflect a first range of radiation wavelengths back into the first solar cell and the second Bragg reflector is operable to reflect a third range of wavelengths back into the first solar cell, and the first Bragg reflector and the second Bragg reflector are operable to cool the solar cell device by reflecting a second range of radiation wavelengths that are outside the photogeneration wavelength range of the first solar cell or that are weakly absorbed by the first solar cell.

MONOLITHIC INTEGRATION OF III-V CELLS FOR POWERING MEMORY ERASURE DEVICES
20170200684 · 2017-07-13 ·

A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (CMOS); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.

Structures for Increased Current Generation and Collection in Solar Cells with Low Absorptance and/or Low Diffusion Length

The present disclosure generally relates to a solar cell device that includes a substrate comprising a front side surface and a backside surface; an epitaxial region overlying the substrate, wherein the epitaxial region comprises a first Bragg reflector disposed below a first solar cell, wherein the first solar cell has a first bandgap, wherein the first Bragg reflector is operable to reflect a first range of radiation wavelengths back into the first solar cell, and is operable to cool the solar cell device by reflecting a second range of radiation wavelengths that are outside the photogeneration wavelength range of the first solar cell or that are weakly absorbed by the first solar cell, and may additionally comprise a second Bragg reflector operable to reflect a third range of radiation wavelengths back into the first solar cell.

STACK-LIKE MULTI-JUNCTION SOLAR CELL

A multi-junction solar cell having at least three partial cells having an emitter and a base. The first partial cell comprises a first layer of a compound containing at least the elements GaInP, and the energy band gap of the first layer is greater than 1.75 eV, and wherein the second partial cell has a second layer of a compound having at least the elements GaAs and the lattice constant of the second layer is in the range between 5.635 and 5.675 , and wherein the third partial cell has a third layer of a compound having at least the elements GaInAs and the energy band gap of the third layer is smaller than 1.25 eV and the lattice constant of the third layer is greater than 5.700 .

Textured metallic back reflector

Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands. In another embodiment, a textured metallic back reflector includes an array of metallic islands disposed on a gallium arsenide material, a plurality of apertures disposed between the metallic islands and extending into the gallium arsenide material, a metallic reflector layer disposed over the metallic islands, and a plurality of reflector protrusions formed between the metallic islands and extending from the metallic reflector layer and into the apertures formed in the gallium arsenide material.