Monolithic multi-dimensional integrated circuits and memory architecture are provided. Exemplary integrated circuits comprise an electronic board having a first side and a second side, a multi-dimensional electronic package having multiple planes, and one or more semiconductor wafers mounted on the first side and the second side of the electronic board and on the multiple planes of the electronic package. Exemplary monolithic multi-dimensional memory architecture comprises one or more tiers, one or more monolithic inter-tier vias spanning the one or more tiers, at least one multiplexer disposed in one of the tiers, and control logic determining whether memory cells are active and which memory cells are active and controlling usage of the memory cells based on such determination. Each tier has a memory cell, and the inter-tier vias act as crossbars in multiple directions. The multiplexer is communicatively coupled to the memory cell in the respective tier. In exemplary embodiments, the one or more semiconductor wafers include one or more solar cells. The solar cells may comprise MEMS and/or on-chip solar cells.

A solar cell is provided, including a substrate having a first surface and a second surface opposite to each other, an emitter formed on the first surface of the substrate and including a textured structure on a side away from the first surface, a passivation structure formed on the textured structure, first electrodes penetrating the passivation structure and in electrical contact with the textured structure of the emitter, and conductive eutectic layers each formed between a respective first electrode and the emitter and including first conductive particles and second conductive particles. Each of the first conductive particles has a shape different from a shape of any of the second conductive particles. The first conductive particles and the second conductive particles have a first number, the first conductive particles have a second number, and a ratio of the second number to the first number in a range of 20% to 80%.

The present invention relates to multi-cell devices fabricated on a common substrate that are more desirable than single cell devices, particularly in photovoltaic applications. Multi-cell devices operate with lower currents, higher output voltages, and lower internal power losses. Prior art multi-cell devices use physical isolation to achieve electrical isolation between cells. In order to fabricate a multicell device on a common substrate, the individual cells must be electrically isolated from one another. In the prior art, isolation generally required creating a physical dielectric barrier between the cells, which adds complexity and cost to the fabrication process. The disclosed invention achieves electrical isolation without physical isolation by proper orientation of interdigitated junctions such that the diffusion fields present in the interdigitated region essentially prevent the formation of a significant parasitic current which would be in opposition to the output of the device.

The present technology relates to multi-cell devices fabricated on a common substrate that are more desirable than single cell devices, particularly in photovoltaic applications. Multi-cell devices operate with lower currents, higher output voltages, and lower internal power losses. Prior art multi-cell devices use physical isolation to achieve electrical isolation between cells. In order to fabricate a multicell device on a common substrate, the individual cells must be electrically isolated from one another. In the prior art, isolation generally required creating a physical dielectric barrier between the cells, which adds complexity and cost to the fabrication process. The disclosed technology achieves electrical isolation without physical isolation by proper orientation of interdigitated junctions such that the diffusion fields present in the interdigitated region essentially prevent the formation of a significant parasitic current which would be in opposition to the output of the device.

Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. In an example, a solar cell includes a substrate. A plurality of alternating N-type and P-type semiconductor regions is disposed in or above the substrate. A conductive contact structure is disposed above the plurality of alternating N-type and P-type semiconductor regions. The conductive contact structure includes a plurality of metal seed material regions providing a metal seed material region disposed on each of the alternating N-type and P-type semiconductor regions. A metal foil is disposed on the plurality of metal seed material regions, the metal foil having anodized portions isolating metal regions of the metal foil corresponding to the alternating N-type and P-type semiconductor regions.

Process for manufacturing a photovoltaic module placed on an emissive display device, said photovoltaic module comprising an array containing a plurality of photovoltaic cells and a plurality of transparent zones called orifices, and said photovoltaic module comprising an array of optical elements able to focus, by refraction or reflection, the light emitted by the device into the orifices.

A solar cell module is disclosed. The solar cell module includes a plurality of solar cells, a front transparent substrate located in a front surface of the plurality of solar cells, a back transparent substrate located on a back surface of the plurality of solar cells, a front protection unit located between the front transparent substrate and the plurality of solar cells, and a back protection unit located between the back transparent substrate and the plurality of solar cells. The back transparent substrate includes an anti-reflection layer.

A solar panel array includes a plurality of sub-arrays of solar panels. For each sub-array, the solar panels are electrically connected in series, have unequal shapes, and have equal areas.

A method for producing a thin-film solar cell on an initial substrate, the thin-film solar cell being removable from the initial substrate, the thin-film solar cell including a rear metal layer and a thin-film stack including a p-n junction, the method including depositing the rear metal layer on the initial substrate by sputtering; forming the thin-film stack on the rear metal layer, wherein the power, temperature and pressure used to deposit the rear metal layer are chosen so as to introduce shear stress into the rear metal layer in a controlled manner.

Methods are disclosed for assembling PV modules using connectors that have strain relief elements. Strings can be inspected individually and dimensional information can be obtained to layup the strings into a PV module in a specific manner. Portions of the strings can be soldered using elevators to lift connectors into place, and then applying heat to both sides of the connector.