Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

A dual vertical transfer gate, a transistor including the same, and a CMOS image sensing device including the same. In some embodiments, a gate of the dual vertical transfer transistor may include a pair of poles, which are extended to an n-type region of a photodiode, and a connecting portion, which connects the paired poles to each other. A first insulating pattern may be provided between the poles and on the substrate.

An imaging device and a semiconductor device that can reduce the capacitance of a gate electrode are provided. The imaging device includes a photoelectric conversion element and a semiconductor device that reads charge generated by the photoelectric conversion element. The semiconductor device includes a semiconductor substrate and a field-effect transistor provided on the first surface side of the semiconductor substrate. The field-effect transistor includes a gate electrode including a buried gate portion buried from the first surface of the semiconductor substrate toward an inside of the semiconductor substrate, a gate insulating film disposed between the semiconductor substrate and the gate electrode, a source region provided on the semiconductor substrate and connected to one side of the gate electrode in a gate length direction of the gate electrode, and a drain region connected to the other side of the gate electrode in the gate length direction. The buried gate portion includes a first site, and a second site located between at least one of the source region and the drain region and the first region, and having a thickness from the first surface smaller than that of the first region.

A detection device includes: a substrate; photoelectric conversion elements provided to the substrate; transistors; and signal lines each of which is between adjacent photoelectric conversion elements. Each detection element includes one of the photoelectric conversion element and the transistors adjacent to the photoelectric conversion element. A first signal line among the signal lines is between the photoelectric conversion element of a first detection element and the photoelectric conversion element of a second detection element adjacent to one side of the first detection element and is coupled to the first detection element and the second detection element. A second signal line among the signal lines is between the photoelectric conversion element of the first detection element and the photoelectric conversion element of a third detection element adjacent to another side of the first detection element and is coupled to the first detection element and the third detection element.

Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate.

To reduce an impact due to dry etching performed when a via is formed in a substrate. A first base substrate includes first and second semiconductor substrates. A pixel region is formed on the first semiconductor substrate. A logic circuit that processes a pixel signal output from the pixel region is formed on the second semiconductor substrate. The first base substrate includes a first via that passes through a wiring layer of the logic circuit to a back surface of the first base substrate. A second base substrate includes a connection portion and a second via. The connection portion is connected to the first via of the first base substrate on a front surface of the second base substrate. The connection portion and an electrode situated in a lowest surface of the second base substrate are electrically connected to each other through the second via using a conductive material.

A uniform bridge gradient (UBG) time-of-flight (ToF) photodiode block is described, such as for integration with image sensor pixels. The UBG ToF photodiode block can be part of a UBG ToF pixel, and an image sensor can include an array of such pixels. Each UGB ToF photosensor block has multiple taps for selective activation, and a photodiode region designed for complete and rapid transit of photocarriers, as they are generated, via the multiple taps. Embodiments of the photodiode region include a photodiode-defining implant, a relatively shallow first bridging implant, and relatively deep second bridging implant. The bridging implants provide lateral bridging with a uniform doping gradient near and across the multiple taps.

An image sensor including a plurality of avalanche photodiodes formed inside and on top of a semiconductor substrate of a first conductivity type having a front side and a back side, wherein: trenches vertically extend in the substrate from its front side to its back side, the trenches having, in top view, the shape of a continuous grid laterally delimiting a plurality of substrate islands, each island defining a pixel including a single individually-controllable avalanche photodiode, and including a doped area of collection of an avalanche signal of the pixel photodiode the lateral walls of the trenches are coated with a first semiconductor layer having a conductivity type opposite to that of the collection area, and a conductive region extends in the trenches, the conductive region being in contact with the surface of the first semiconductor layer opposite to the substrate.

Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.