A dual vertical transfer gate, a transistor including the same, and a CMOS image sensing device including the same. In some embodiments, a gate of the dual vertical transfer transistor may include a pair of poles, which are extended to an n-type region of a photodiode, and a connecting portion, which connects the paired poles to each other. A first insulating pattern may be provided between the poles and on the substrate.

An imaging device and a semiconductor device that can reduce the capacitance of a gate electrode are provided. The imaging device includes a photoelectric conversion element and a semiconductor device that reads charge generated by the photoelectric conversion element. The semiconductor device includes a semiconductor substrate and a field-effect transistor provided on the first surface side of the semiconductor substrate. The field-effect transistor includes a gate electrode including a buried gate portion buried from the first surface of the semiconductor substrate toward an inside of the semiconductor substrate, a gate insulating film disposed between the semiconductor substrate and the gate electrode, a source region provided on the semiconductor substrate and connected to one side of the gate electrode in a gate length direction of the gate electrode, and a drain region connected to the other side of the gate electrode in the gate length direction. The buried gate portion includes a first site, and a second site located between at least one of the source region and the drain region and the first region, and having a thickness from the first surface smaller than that of the first region.

To provide a semiconductor device and an imaging apparatus capable of improving performance of a transistor. The semiconductor device includes a semiconductor substrate and a transistor provided on the semiconductor substrate. A gate electrode of the transistor includes a first part disposed at a position opposing the semiconductor substrate via a gate insulating film of the transistor and configured to form a channel on the semiconductor substrate and a second part positioned on top of the first part and configured to have a smaller contribution toward the formation of the channel than the first part. The first part includes a gate end which is positioned on a side of one region of a drain region and a source region of the transistor and in which an electric field concentrates with respect to the one region. The gate end is positioned above or below a surface of the one region via a stepped portion provided on a side of a first surface of the semiconductor substrate and is flush with a side surface of the second part.

An image sensor includes: a semiconductor substrate including a first surface and a second surface opposite to each other; a buried transfer gate electrode arranged in a transfer gate trench extending from the first surface of the semiconductor substrate into the semiconductor substrate, wherein the buried transfer gate electrode has an upper surface arranged at a level lower than that of the first surface of the semiconductor substrate with respect to the second surface of the semiconductor substrate; and a transfer gate spacer arranged on an upper sidewall of the transfer gate trench and on the buried transfer gate electrode.

The present disclosure discloses a flat panel detector, a driving method, a driving device and a flat panel detection device. The flat panel detector includes: a base substrate, and a plurality of detection units located on the base substrate; each of the detection units includes a photodiode and a detection transistor; the flat panel detector further includes: a compensation semiconductor material layer including a plurality of compensation structures mutually spaced; each detection transistor is correspondingly provided with a compensation structure, and the compensation structure is located between a gate and a gate insulating layer of the corresponding detection transistor.

An image sensor includes a substrate having a plurality of pixel regions and a deep device isolation pattern disposed in the substrate between the pixel regions. The pixel regions include first, second, third, and fourth pixel regions, which are adjacent to each other in first and second directions. The deep device isolation pattern includes first portions interposed between the first and second pixel regions and between the third and fourth pixel regions and spaced apart from each other in the second direction, and second portions interposed between the first and third pixel regions and between the second and fourth pixel regions and spaced apart from each other in the first direction. The first pixel region includes a first extended active pattern, which is extended to the second pixel region in the first direction and is disposed between the first portions of the deep device isolation pattern.

Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.

Color router based photodiodes and integrated pixel circuit. In one embodiment, a plurality of pixels arranged in rows and columns of a pixel array are disposed in a semiconductor material. In some embodiments, each pixel comprises a plurality of photodiodes and a color router covering the plurality of photodiodes. In some embodiments, the plurality of pixels is configured to receive an incoming light through the color router. In some embodiments, the integrated pixel circuit includes a plurality of pixel circuits, where each pixel circuit is associated with a corresponding pixel of the plurality of pixels. In some embodiments, the pixel circuits are configured on a same horizontal plane as the plurality of photodiodes.

An image sensor includes a photodiode disposed in a substrate and including an n-type impurity region, wherein the n-type impurity region is doped with n-type impurities, a transfer gate (TG) structure partially buried in the substrate and disposed on the n-type impurity region, a recess disposed at an upper surface of the substrate and being spaced apart from the TG structure, a floating diffusion (FD) region disposed under the recess and doped with n-type impurities, and an impurity region disposed at a portion of the substrate between the TG structure and the recess and doped with p-type impurities. An upper surface of the FD region is lower than an upper surface of the impurity region.