A voltage to be applied to a charge holding section to which charges generated by a plurality of photoelectric conversion sections are transferred is adjusted. An imaging element includes a plurality of photoelectric conversion sections, a charge holding section, a plurality of charge transfer sections, an image signal generation section, and a plurality of capacitive coupling wirings. The photoelectric conversion section performs photoelectric conversion of incident light to generate a charge. The charge holding section holds the generated charge. The charge transfer section is arranged for each photoelectric conversion section and transfers the generated charge to the charge holding section. The image signal generation section generates an image signal corresponding to the held electric charge. The capacitive coupling wirings are capacitively coupled to the charge holding section, and are individually applied with an adjustment signal for adjusting the potential of the charge holding section.

Disclosed are image sensors and methods of fabricating the same. The image sensor includes a semiconductor substrate including a pixel zone and a pad zone and having a first surface and a second surface opposing each other, a first pad separation pattern on the pad zone and extending from the first surface of the semiconductor substrate toward the second surface of the semiconductor substrate, a second pad separation pattern extending from the second surface toward the first surface of the semiconductor substrate on the pad zone the second pad and in contact with the first pad separation pattern, and a pixel separation pattern on the pixel zone and extending from the second surface of the semiconductor substrate toward the first surface of the semiconductor substrate.

An image sensor includes a substrate having a plurality of pixel regions and a deep device isolation pattern disposed in the substrate between the pixel regions. The pixel regions include first, second, third, and fourth pixel regions, which are adjacent to each other in first and second directions. The deep device isolation pattern includes first portions interposed between the first and second pixel regions and between the third and fourth pixel regions and spaced apart from each other in the second direction, and second portions interposed between the first and third pixel regions and between the second and fourth pixel regions and spaced apart from each other in the first direction. The first pixel region includes a first extended active pattern, which is extended to the second pixel region in the first direction and is disposed between the first portions of the deep device isolation pattern.

The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Color router based photodiodes and integrated pixel circuit. In one embodiment, a plurality of pixels arranged in rows and columns of a pixel array are disposed in a semiconductor material. In some embodiments, each pixel comprises a plurality of photodiodes and a color router covering the plurality of photodiodes. In some embodiments, the plurality of pixels is configured to receive an incoming light through the color router. In some embodiments, the integrated pixel circuit includes a plurality of pixel circuits, where each pixel circuit is associated with a corresponding pixel of the plurality of pixels. In some embodiments, the pixel circuits are configured on a same horizontal plane as the plurality of photodiodes.

Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.

The present technology relates to a solid-state imaging device, a driving method therefor, and an electronic apparatus capable of acquiring a signal to detect phase difference and a signal to generate a high dynamic range image at the same time. The solid-state imaging device includes a pixel array unit in which a plurality of pixels that receives light of a same color is arranged under one on-chip lens. The plurality of pixels uses at least one pixel transistor in a sharing manner, some pixels out of the plurality of pixels are set to have a first exposure time, and other pixels are set to have a second exposure time shorter than the first exposure time. The present technology can be applied to, for example, a solid-state imaging device or the like.

An image sensor comprises a first and second chips. The first chip includes a first semiconductor substrate, a photoelectric conversion layer in the first semiconductor substrate, a color filter, a micro lens, a first transistor adjacent to the photoelectric conversion layer, a first insulating layer, and a first metal layer in the first insulating layer and connected to the first transistor. The second chip includes a second insulating layer, a second semiconductor substrate, a second transistor on the second semiconductor substrate, a second metal layer in the second insulating layer and connected to a gate structure of the second transistor through a gate contact, a landing metal layer below the second metal layer, and a through via in direct contact with the landing metal layer and vertically passing through the second semiconductor substrate. A width of the through via becomes narrower as the width approaches the third surface.

A photoelectric conversion apparatus includes a first conductive line that is arranged in a first wiring layer and connects a floating diffusion to a gate of an amplification transistor, a shielding portion that is made of metal and provided in a second wiring layer which is an upper layer of the first wiring layer such that at least one portion of the shielding portion overlaps the first conductive line in a plan view, and a second conductive line that is arranged on a third wiring layer which is an upper layer of the second wiring layer such that at least one portion of the second conductive line overlaps the first conductive line in the plan view. The shielding portion includes a plurality of insulation portions in the plan view.