A device for producing electrical current. In one embodiment, the device comprises a stack of epitaxial layers (from a bottom surface): a p-doped semiconductor reflector layer, a p-doped semiconductor emitter layer, an n-doped semiconductor base layer, and an n-doped semiconductor window layer. A radioisotope source, disposed above or in contact with an uppermost layer of the stack, produces radioisotope decay particles or gamma rays that impinge the stack. The electrical current is produced between the first and second conductive regions by action of the radioisotope decay particles or the gamma rays on the emitter and base layers.

A photodiode, such as a linear mode avalanche photodiode can be made free of excess noise via having a superlattice multiplication region that allows only one electrical current carrier type, such as an electron or a hole, to accumulate enough kinetic energy to impact ionize when biased, where the layers are lattice matched. A photodiode can be constructed with i) a lattice matched pair of a first semiconductor alloy and a second semiconductor alloy in a superlattice multiplication region, ii) an absorber region, and iii) a semiconductor substrate. A detector with multiple photodiodes can be made with these construction layers in order to have a cutoff wavelength varied anywhere from 1.7 to 4.9 m as well as a noise resulting from a dark current at a level such that an electromagnetic radiation signal with the desired minimum wavelength cutoff can be accurately sensed by the photodiode.

A camera having an integrated dewar cooler assembly (IDCA) with an optical window, and a reduced dark current photodetector disposed within the IDCA to receive light passing through the optical window. The photodetector comprising a semiconductor photo absorbing layer, a semiconductor barrier layer having a thickness and a first side adjacent a side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the photo absorbing layer and a conduction band energy level exhibiting an energy gap in relation to the conduction band of the photo absorbing layer, and a contact area comprising a doped semiconductor, the contact area is adjacent a second side of the barrier layer opposing the first side. The energy gap and/or the thickness of the of the barrier layer is sufficient to minimize charge carriers tunneling and thermalization.

An infrared detector and a method for forming it are provided. The detector includes absorber, barrier, and contact regions. The absorber region includes a first semiconductor material, with a first lattice constant, that produces charge carriers in response to infrared light. The barrier region is disposed on the absorber region and comprises a superlatice that includes (i) first barrier region layers comprising the first semiconductor material, and (ii) second barrier region layers comprising a second semiconductor material, different from, but lattice matched to, the first semiconductor material. The first and second barrier region layers are alternatingly arranged. The contact region is disposed on the barrier region and comprises a superlattice that includes (i) first contact region layers comprising the first semiconductor material, and (ii) second contact region layers comprising the second semiconductor material layer. The first and second contact region layers are alternatingly arranged.

A method of fabricating multijunction solar cell including an upper solar subcell and having an emitter of p conductivity type with a first band gap, and a base of n conductivity type with a second band gap greater than the first band gap; a lower solar subcell disposed below the upper solar subcell having an emitter of p conductivity type with a third band gap, and a base of n conductivity type with a fourth band gap greater than the third band gap; and an intermediate grading interlayer disposed between the upper and lower solar subcells and having a graded lattice constant that matches the upper first subcell on a first side and the second solar subcell on the second side opposite the first side, and having a fifth band gap that is greater than the second band gap of the upper solar subcell.

In one aspect, an avalanche photodiode, includes an absorber, a first superlattice structure directly connected to the absorber and configured to multiply holes and a second superlattice structure directly connected to the first superlattice structure and configured to multiply electrons. The first and second superlattice structures include III-V semiconductor material. The avalanche photodiode is a dual mode device configured to operate in either a linear mode or a Geiger mode. In another aspect, a method includes fabricating the avalanche diode.

The present disclosure provides methods of fabricating a multijunction solar cell panel in which one or more of the steps are performed using an automated process. In some embodiments, the automated process uses machine vision.

Certain embodiments of the present invention may be directed to a transistor structure. The transistor structure may include a semiconductor substrate. The semiconductor substrate may include a drift region, a collector region, an emitter region, and a lightly-doped/undoped region. The lightly-doped/undoped region may be lightly-doped and/or undoped. The transistor structure may also include a heterostructure. The heterostructure forms a heterojunction with the lightly-doped/undoped region. The transistor structure may also include a collector terminal. The collector terminal is in contact with the collector region. The transistor structure may also include a gate terminal. The gate terminal is in contact with the heterostructure. The transistor structure may also include an emitter terminal. The emitter terminal is in contact with the lightly-doped/undoped region and the emitter region.

A method of forming a layered OP material is provided, where the layered OP material comprises an OPGaAs template, and a layer of GaP on the OPGaAs template. The OPGaAs template comprises a patterned layer of GaAs having alternating features of inverted crystallographic polarity of GaAs. The patterned layer of GaAs comprises a first feature comprising a first crystallographic polarity form of GaAs having a first dimension, and a second feature comprising a second crystallographic polarity form of GaAs having a second dimension. The layer of GaP on the patterned layer of GaAs comprises alternating regions of inverted crystallographic polarity that generally correspond to their underlying first and second features of the patterned layer of GaAs. Additionally, each of the alternating regions of inverted crystallographic polarity of GaP are present at about 100 micron thickness or more.

A uni-terminal transistor device is described. In one embodiment, an n-channel transistor having p-terminal characteristics comprises a first semiconductor layer having a discrete hole level; a second semiconductor layer having a conduction band whose minimum level is lower than that of the first semiconductor layer; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level below the minimum level of the conduction band of the second semiconductor layer for zero bias applied to the gate metal layer and to obtain p-terminal characteristics.