Patent classifications
H10F77/1246
OPTICALLY CONTROLLED SEMICONDUCTOR DEVICES
Described herein is a semiconductor structure, comprising: a drain region; a drift region comprised of a wide band gap material disposed over the drain region; and a channel structure disposed over the drift region. In some embodiments, the channel structure comprises: an optically active material disposed over the drift region, wherein the optically active material generates charge carriers in response to an optical signal; and a source region disposed over the optically active material, wherein in an off state charge carriers in the optically active material are depleted to turn off the semiconductor structure, and in an on state charge carriers in the optically active material conduct a current in the semiconductor structure when an electric field is applied across the source region and drain region, causing the current to substantially flow directly between the source region and the drain region.
P-type contact to semiconductor heterostructure
A contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer. A light generating structure formed over the n-type semiconductor contact layer has a set of quantum wells and barriers configured to emit or absorb target radiation. An ultraviolet transparent semiconductor layer having a non-uniform thickness is formed over the light generating structure. A p-type contact semiconductor layer having a non-uniform thickness is formed over the ultraviolet transparent semiconductor layer.
TECHNIQUES FOR FORMING OPTOELECTRONIC DEVICES
Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate are described. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise (111) single crystal silicon. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices.
Optoelectronic Semiconductor Chip and Method for Fabrication Thereof
An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a first semiconductor layer sequence having a plurality of microdiodes, and a second semiconductor layer sequence having an active region. The first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material, the first semiconductor layer sequence is before the first semiconductor layer sequence in the direction of growth, and the microdiodes form an ESD protection for the active region.
Photodetector with nanowire photocathode
A photodetector assembly for ultraviolet and far-ultraviolet detection includes an anode, a microchannel plate with an array of multichannel walls, and a photocathode layer disposed on the microchannel plate. Additionally, the photocathode may include nanowires deposited on a top surface of the array of multichannel walls.
InGaN/GaN multiple quantum well blue light detector combined with embedded electrode and passivation layer structure and preparation method and application thereof
An InGaN/GaN multiple quantum well blue light detector- includes: a Si substrate, an AlN/AlGaN/GaN buffer layer, a u-GaN/AlN/u-GaN/SiN.sub.x/u-GaN buffer layer, an n-GaN buffer layer, an InGaN/GaN superlattice layer and an InGaN/GaN multiple quantum well layer in sequence from bottom to top. The multiple quantum well layer has a groove and a mesa, the mesa and the groove of the multiple quantum well layer are provided with a Si.sub.3N.sub.4 passivation layer. The passivation layer in the groove is provided with a first metal layer electrode with a semicircular cross section, and the passivation layer on the mesa is provided with second metal layer electrode.
Method of producing an optoelectronic semiconductor chip and an optoelectronic semiconductor chip
A method of producing an optoelectronic semiconductor chip includes providing a growth substrate and a semiconductor layer sequence grown on the growth substrate with a main extension plane including a p-conductive layer, an active zone and an n-conductive layer, removing the semiconductor layer sequence in regions to form at least one aperture extending through the p-conductive layer and the active zone into the n-conductive layer of the semiconductor layer sequence, depositing a protective layer on a side of the semiconductor layer sequence facing away from the growth substrate, depositing an aluminum layer containing aluminum across the entire surface on a side of the semiconductor layer sequence facing away from the growth substrate, removing the growth substrate, and forming a mesa by removing the semiconductor layer sequence at the regions of the protective layer, wherein the protective layer is subsequently freely externally accessible at least in places.
SILICON HETEROJUNCTION PHOTOVOLTAIC DEVICE WITH WIDE BAND GAP EMITTER
A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
HIGH-VOLTAGE SOLID-STATE TRANSDUCERS AND ASSOCIATED SYSTEMS AND METHODS
High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage.
MATERIALS, STRUCTURES, AND METHODS FOR OPTICAL AND ELECTRICAL III-NITRIDE SEMICONDUCTOR DEVICES
The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates. In some embodiments, the present invention provides materials, structures, devices, and methods for acoustic wave devices and technology, including epitaxial and non-epitaxial piezoelectric materials and structures useful for acoustic wave devices. In some embodiments, the present invention provides metal-base transistor devices, structures, materials and methods of forming metal-base transistor material structures for use in semiconductor devices.