Patent classifications
H10F77/1642
ULTRATHIN SILICON OXYNITRIDE INTERFACE MATERIAL, TUNNEL OXIDE PASSIVATED STRUCTURE AND PREPARATION METHODS AND APPLICATIONS THEREOF
An ultrathin silicon oxynitride interface material, a tunnel oxide passivated structure and preparation methods and applications thereof are provided. The ultrathin silicon oxynitride interface material is an SiON film with a thickness of 1 nm to 4 nm, and the percentage content of N atoms is 1% to 40%. Compared with silicon oxide, the diffusion rate of boron in the SiON film of the present disclosure is low, which effectively reduces the damaging effect of boron, improves the integrity of the SiON film and maintains the chemical passivation effect. The SiON film with high nitrogen concentration can noticeably lower the concentration of boron on the silicon surface so as to lessen the boron-induced defects. Furthermore, the SiON film has an energy band structure approximate to silicon nitride, which increases the hole transport efficiency and hole selectivity, and further improves the passivation quality and reduces the contact resistivity.
SOLAR CELL AND MANUFACTURING METHOD THEREOF, AND PHOTOVOLTAIC SYSTEM
A solar cell and a manufacturing method thereof, and a photovoltaic system. The solar cell includes: a substrate layer including a first surface and a second surface arranged oppositely along a thickness direction thereof; a tunnel oxide layer, a first doped polysilicon layer, and a first passivation layer sequentially arranged on the first surface of the substrate layer in a direction gradually away from the substrate layer; and a first finger electrode layer, at least one of the first fingers being arranged in first connection holes, bottoms of the first connection holes being located in the first doped polysilicon layer, and the first fingers passing through the first connection holes corresponding thereto to be electrically connected to the first doped polysilicon layer; and in the first direction, widths of the first connection holes being all less than widths of the first fingers corresponding to the first connection holes. While ensuring good electrical connection, the solar cell causes less damage and recombination to a passivation structure of the solar cell, and has high photoelectric conversion efficiency.
Semiconductor substrate, solar cell, and photovoltaic module
A semiconductor substrate, including a back surface having N-type conductive regions and P-type conductive regions. The N-type conductive regions are provided with first non-pyramidal texture structures, and the P-type conductive regions are provided with second non-pyramidal texture structures. A top surface of the first non-pyramidal texture structure is a polygonal plane, and a top surface of the second non-pyramidal texture structure is a polygonal plane. A one-dimensional size of the top surface of the first non-pyramidal texture structure is less than a one-dimensional size of the top surface of the second non-pyramidal texture structure. The one-dimensional size of the top surface of the first non-pyramidal texture structure is in a range of 5 m to 12 m. The one-dimensional size of the top surface of the second non-pyramidal texture structure is in a range of 10 m to 40 m.
DOUBLE-SIDED PASSIVATED CONTACT CELL AND PREPARATION METHOD THEREOF
The present disclosure provides a double-sided passivated contact cell, where a front side and a rear side of the double-sided passivated contact cell each are provided with a tunnel layer, a doped polysilicon layer, and a passivation layer sequentially from an inside to an outside; and for the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side, one of the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side is a boron and carbon co-doped polysilicon layer, and the other of the doped polysilicon layer at the front side and the doped polysilicon layer at the rear side is a phosphorus and carbon co-doped polysilicon layer. The present disclosure further provides a preparation method of the double-sided passivated contact cell.
METHOD AND OPTOELECTRONIC STRUCTURE PROVIDING POLYSILICON PHOTONIC DEVICES WITH DIFFERENT OPTICAL PROPERTIES IN DIFFERENT REGIONS
Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.
Ultrananocrystalline diamond contacts for electronic devices
A method of forming electrical contacts on a diamond substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of gases. The mixture of gases include a source of a p-type or an n-type dopant. The plasma ball is disposed at a first distance from the diamond substrate. The diamond substrate is maintained at a first temperature. The plasma ball is maintained at the first distance from the diamond substrate for a first time, and a UNCD film, which is doped with at least one of a p-type dopant and an n-type dopant, is disposed on the diamond substrate. The doped UNCD film is patterned to define UNCD electrical contacts on the diamond substrate.
System and method for mass-production of high-efficiency photovoltaic structures
One embodiment of the invention can provide a system for fabricating a photovoltaic structure. During fabrication, the system can form a sacrificial layer on a first side of a Si substrate; load the Si substrate into a chemical vapor deposition tool, with the sacrificial layer in contact with a wafer carrier; and form a first doped Si layer on a second side of the Si substrate. The system subsequently can remove the sacrificial layer; load the Si substrate into a chemical vapor deposition tool, with the first doped Si layer facing a wafer carrier; and form a second doped Si layer on the first side of the Si substrate.
Method of fabricating double sided Si(Ge)/Sapphire/III-nitride hybrid structure
One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.
TRENCH PROCESS AND STRUCTURE FOR BACKSIDE CONTACT SOLAR CELLS WITH POLYSILICON DOPED REGIONS
A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
SCREEN PRINTING ELECTRICAL CONTACTS TO NANOSTRUCTURED AREAS
A process is provided for contacting a nanostructured surface. The process may include (a) providing a substrate having a nanostructured material on a surface, (b) passivating the surface on which the nanostructured material is located, (c) screen printing onto the nanostructured surface and (d) firing the screen printing ink at a high temperature. In some embodiments, the nanostructured material compromises silicon. In some embodiments, the nanostructured material includes silicon nanowires. In some embodiments, the nanowires are around 150 nm, 250 nm, or 400 nm in length. In some embodiments, the nanowires have a diameter range between about 30 nm and about 200 nm. In some embodiments, the nanowires are tapered such that the base is larger than the tip. In some embodiments, the nanowires are tapered at an angle of about 1 degree, about 3 degrees, or about 10 degrees. In some embodiments, a high temperature can be approximately 700 C, 750 C, 800 C, or 850 C.