Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

This application is directed to a low cost IC solution that provides Super CMOS microelectronics macros. Hereinafter, SCMOS refers to Super CMOS and Schottky CMOS. SCMOS device solutions includes a niche circuit element, such as complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co, Ti, Ni or other metal atoms or compounds) to P- and N- Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form (i) generic logic gates, (ii) functional blocks of microprocessors and microcontrollers such as but not limited to data paths, multipliers, muliplier-accumaltors, (ii) memory cells and control circuits of various types (SRAM's with single or multiple read/write port(s), binary and ternary CAM's), (iii) multiplexers, crossbar switches, switch matrices in network processors, graphics processors and other processors to implement a variety of communication protocols and algorithms of data processing engines for (iv) Analytics, (v) block-chain and encryption-based security engines (vi) Artificial Neural Networks with specific circuits to emulate or to implement a self-learning data processor similar to or derived from the neurons and synapses of human or animal brains, (vii) analog circuits and functional blocks from simple to the complicated including but not limited to power conversion, control and management either based on charge pumps or inductors, sensor signal amplifiers and conditioners, interface drivers, wireline data transceivers, oscillators and clock synthesizers with phase and/or delay locked loops, temperature monitors and controllers; all the above are built from discrete components to all grades of VLSI chips. Solar photovoltaic electricity conversion, bio-lab-on-a-chip, hyperspectral imaging (capture/sensing and processing), wireless communication with various transceiver and/or transponder circuits for ranges of frequency that extend beyond a few 100 MHz, up to multi-THz, ambient energy harvesting either mechanical vibrations or antenna-based electromagnetic are newly extended or nacent fields of the SCMOS IC applications.

Provided is a detector that includes a scintillator, a common electrode, a pixel electrode, and a plurality of insulating layers, with a plurality of nano-pillars formed in the plurality of insulating layers, a nano-scale well structure between adjacent nano-pillars, with a-Se separating the adjacent nano-pillars, and a method for operation thereof.

Disclosed is a manufacturing method of a solar cell, including forming a photoelectric converter including an amorphous semiconductor layer, forming an electrode connected to the photoelectric converter, and performing a post-treatment by providing light to the photoelectric converter and the electrode.

A method for treating a stack includes a substrate of n-doped crystalline silicon and a passivation layer of hydrogenated amorphous silicon disposed on a face of the substrate, the method including exposing the stack to electromagnetic radiation during a treatment period (t) less than or equal to 12 s, the electromagnetic radiation having an irradiance (E) greater than or equal to 200 kW/m.sup.2.

Provided is a detector that includes a scintillator, a common electrode, a pixel electrode, and a plurality of insulating layers, with a plurality of nano-pillars formed in the plurality of insulating layers, a nano-scale well structure between adjacent nano-pillars, with a-Se separating the adjacent nano-pillars, and a method for operation thereof.

This application is directed to a low cost IC solution that provides Super CMOS microelectronics macros. Hereinafter, SCMOS refers to Super CMOS and Schottky CMOS. SCMOS device solutions includes a niche circuit element, such as complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co, Ti, Ni or other metal atoms or compounds) to P- and N-Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form (i) generic logic gates, (ii) functional blocks of microprocessors and microcontrollers such as but not limited to data paths, multipliers, muliplier-accumaltors, (ii) memory cells and control circuits of various types (SRAM's with single or multiple read/write port(s), binary and ternary CAM's), (iii) multiplexers, crossbar switches, switch matrices in network processors, graphics processors and other processors to implement a variety of communication protocols and algorithms of data processing engines for (iv) Analytics, (v) block-chain and encryption-based security engines (vi) Artificial Neural Networks with specific circuits to emulate or to implement a self-learning data processor similar to or derived from the neurons and synapses of human or animal brains, (vii) analog circuits and functional blocks from simple to the complicated including but not limited to power conversion, control and management either based on charge pumps or inductors, sensor signal amplifiers and conditioners, interface drivers, wireline data transceivers, oscillators and clock synthesizers with phase and/or delay locked loops, temperature monitors and controllers; all the above are built from discrete components to all grades of VLSI chips. Solar photovoltaic electricity conversion, bio-lab-on-a-chip, hyperspectral imaging (capture/sensing and processing), wireless communication with various transceiver and/or transponder circuits for ranges of frequency that extend beyond a few 100 MHz, up to multi-THz, ambient energy harvesting either mechanical vibrations or antenna-based electromagnetic are newly extended or nacent fields of the SCMOS IC applications.

A solar cell is discussed. The solar cell includes a silicon substrate; a front passivation layer positioned on a front surface of the silicon substrate; an n-doped layer positioned on the front surface of the silicon substrate; an anti-reflection layer positioned on the n-doped layer; a p-doped region positioned on a rear surface of the silicon substrate; an n-doped region positioned on the rear surface of the silicon substrate and spaced apart from the p-doped region; a rear passivation layer positioned on the rear surface of the silicon substrate, the rear passivation layer including: a first portion positioned between the p-doped region and the silicon substrate; a second portion positioned between the n-doped region and the silicon substrate, the second portion being space apart from the first potion; and a third portion disposed between the first portion and the second portion; a first electrode directly contacted to the p-doped region; and a second electrode directly contacted to the n-doped region.

A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.

A hybrid organic-inorganic thin film is provided. The hybrid organic-inorganic thin film comprising: an organic-phase comprising a porous organic nanostructure comprised of an interpenetrating network having at least one dimension between 0.1 and 100 nm; and an inorganic phase at least partially distributed within the porosity of the organic phase. In a first aspect, the organic phase has a first band gap and the inorganic phase has a second band gap different from the first band gap. A method of producing an organic-inorganic energy harvesting device and a device therefrom comprising the hybrid organic-inorganic thin film is provided.