A semiconductor device is provided, which includes a first semiconductor structure, a second semiconductor structure, and an active region. The active region is located between the first semiconductor structure and the second semiconductor structure. The active region includes a light-emitting region having N pair(s) of semiconductor stack(s). Each of the semiconductor stack includes a well layer and a barrier layer, in which N is a positive integer greater than or equal to 1. The well layer includes a first group III-V semiconductor material including indium with a first percentage of indium content. The barrier layer includes a second group III-V semiconductor material including indium with a second percentage of indium content. The first group III-V semiconductor material and the second group III-V semiconductor material further includes phosphorus. The second percentage of indium content is less than the first percentage of indium content.

A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.

A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.

A light-emitting device including an epitaxial layer, a support layer, an insulating layer, a first electrode pad, and a second electrode pad is provided. The epitaxial layer includes a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer, wherein the light-emitting layer is disposed on a partial area of the first type doped semiconductor layer and is between the first type doped semiconductor layer and the second type doped semiconductor layer. The support layer covers the second type doped semiconductor layer while the insulating layer covers the epitaxial layer and the support layer. The first and the second electrode pads are disposed over the insulating layer and electrically connected to the first and the second type doped semiconductor layers, respectively. The support layer extends from a first position below the first electrode pad to a second position below the second electrode pad.

An electronic device includes: a semiconductor layer; a first layer disposed on the semiconductor layer, including at least one of oxygen atoms and nitrogen atoms and having a first maximum thickness; a second layer, wherein the first layer is disposed between the second layer and the semiconductor layer, and the second layer has a second maximum thickness; and a third layer, wherein the second layer is disposed between the first layer and the third layer, the third layer has a third maximum thickness, and the second maximum thickness and the third maximum thickness are greater than the first maximum thickness, wherein the first layer comprises a first position and a second position, the first position is closer to the semiconductor layer than the second position, and a first oxygen atomic percentage at the first position is less than a second oxygen atomic percentage at the second position.

A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

A method for fabricating epitaxial light control features, without reactive ion etching or wet etching, when active layers are included. The epitaxial light control features comprise light extraction or guiding structures integrated on an epitaxial layer of a light emitting device such as a light emitting diode. The light extraction or guiding structures are fabricated on the epitaxial layer using an epitaxial lateral overgrowth (ELO) technique. The epitaxial light control features can have many different shapes and can be fabricated with standard processing techniques, making them highly manufacturable at costs similar to standard processing techniques.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

In an embodiment a method for producing optoelectronic semiconductor devices includes providing at least one optoelectronic semiconductor chip with at least one contact side, generating at least one coating region and at least one protection region on the contact side or on at least one of the contact sides, applying at least one liquid coating material to the at least one contact side, wherein the at least one coating material wets the at least one coating region and does not wet the at least one protection region and solidifying the at least one coating material into at least one electrical contact structure on the at least one coating region such that the semiconductor chip is capable of being energized through the at least one contact structure.

In an embodiment a method for producing optoelectronic semiconductor devices includes providing at least one optoelectronic semiconductor chip with at least one contact side, generating at least one coating region and at least one protection region on the contact side or on at least one of the contact sides, applying at least one liquid coating material to the at least one contact side, wherein the at least one coating material wets the at least one coating region and does not wet the at least one protection region and solidifying the at least one coating material into at least one electrical contact structure on the at least one coating region such that the semiconductor chip is capable of being energized through the at least one contact structure.