Various forms of Mg.sub.xGe.sub.1xO.sub.2x are disclosed, where an epitaxial layer comprises single crystal Mg.sub.xGe.sub.1xO.sub.2x, with x having a value of 0x<1, wherein the single crystal Mg.sub.xGe.sub.1xO.sub.2x has a crystal symmetry compatible with a substrate or with an underlying layer on which the single crystal Mg.sub.xGe.sub.1xO.sub.2x is grown. Semiconductor structures and devices comprising the epitaxial layer of Mg.sub.xGe.sub.1xO.sub.2x are disclosed, along with methods of making the epitaxial layers and semiconductor structures and devices.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

The present disclosure relates to an insect trap using an ultraviolet light-emitting diode (UV LED) lamp, and more particularly, to an insect trap using, in place of a conventional UV light source lamp, a UV LED lamp that significantly increases the insect trapping efficiency. The insect trap according to the present disclosure includes: a UV LED lamp disposed in an air inlet portion of the duct, and including a printed circuit board (PCB) that has a UV LED chip mounted thereon; an installing portion for installing the UV LED lamp on; and a trapping portion provided near the installing portion.

A LED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.

The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

A semiconductor light-emitting device comprises an epitaxial structure for emitting a light and comprises an edge, a first portion and a second portion surrounding the first portion, wherein a concentration of a doping material in the second portion is higher than that of the doping material in the first portion, a main light-extraction surface on the epitaxial structure and comprises a first light-extraction region corresponding to the first portion and a second light-extraction region corresponding to the second portion and an edge, wherein the second portion is between the edge and the first portion.

The present disclosure relates to an insect trap using an ultraviolet light-emitting diode (UV LED) lamp, and more particularly, to an insect trap using, in place of a conventional UV light source lamp, a UV LED lamp that significantly increases the insect trapping efficiency. The insect trap according to the present disclosure includes: a UV LED lamp disposed in an air inlet portion of the duct, and including a printed circuit board (PCB) that has a UV LED chip mounted thereon; an installing portion for installing the UV LED lamp on; and a trapping portion provided near the installing portion.

A light-emitting device is provided. The light-emitting device comprises: an active structure, the active structure comprising alternate well layers and barrier layers, wherein each of the well layers comprises multiple different elements of group VA; a first semiconductor layer of first conductivity type and a second semiconductor layer of second conductivity type sandwiching the active structure; an intermediate layer interposed between the first semiconductor layer and the active structure; and a first window layer on the first semiconductor layer, wherein the intermediate layer comprises Al.sub.z1Ga.sub.1-z1As, the first window layer comprises Al.sub.z2Ga.sub.1-z2As, and z.sub.1>z.sub.2.