Inhibition of movement of charges in a semiconductor element formed by growing a group III-V compound semiconductor layer on a silicon substrate is prevented. The semiconductor element includes a silicon substrate, a first compound semiconductor layer, a second compound semiconductor layer, and an electrode. The first compound semiconductor layer is formed on the silicon substrate. The second compound semiconductor layer is stacked on the first compound semiconductor layer. The electrode is disposed on the silicon substrate and controls movement of charges between the silicon substrate and the second compound semiconductor layer via the first compound semiconductor layer.

A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl.sub.xN.sub.y material at least partially contiguous with the semiconductor structure. The TiAl.sub.xN.sub.y material can be TiAl.sub.3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAl.sub.xN.sub.y material, such that the TiAl.sub.xN.sub.y material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly current injection structures for LED chips are disclosed. Current injection structures include integrated layers or materials with high work functions as part of contact structures for epitaxial layers of active LED structures. Exemplary structures provide high work function contact layers for p-type epitaxial layers to enhance hole mobility and transport. Further contact structures include combinations of high work function layers with other current spreading layers. Exemplary materials for high work function layers include transition metal oxides.

The disclosure provides a light emitting element array, a display device, and a method of manufacturing the display device. A light emitting element array includes a base substrate, each of a plurality of light emitting elements including a light emitting element rod including a third semiconductor layer, a second semiconductor layer, a light emitting layer, and a first semiconductor layer sequentially stacked on the base substrate and an insulating layer surrounding the light emitting element rod and a connection electrode disposed on the first semiconductor layer of each of the plurality of light emitting elements, wherein a diameter of the connection electrode is greater than a diameter of the light emitting element, and the connection electrode surrounds a side surface of the first semiconductor layer and a side surface of the light emitting layer.

The present disclosure discloses a display substrate, including a substrate, and a driver circuit, an insulation layer and a bonding electrode sequentially superposed on the substrate. The bonding electrode is configured to be connected to an anode and a cathode of a micro inorganic light-emitting diode chip to be bonded. The display substrate further includes an elastic layer sandwiched between the bonding electrode and the insulation layer, the elastic layer having an orthographic projection on the substrate covering at least an orthographic projection of the bonding electrode on the substrate. The present disclosure provides a display panel, including the above display substrate, and further including a micro inorganic light-emitting diode chip having an anode and a cathode thereof connected to the bonding electrode on the display substrate.

A display panel includes a substrate, first bonding electrodes, connecting leads, an electrode carrier plate and second bonding electrodes. The substrate includes a display surface, a non-display surface, and a selected side face. The display surface includes a first bonding area, and the non-display surface includes a second bonding area. The first bonding electrodes are arranged side by side at the intervals in the first bonding area. The connecting leads are arranged side by side at intervals, each connecting lead includes a first portion, a second portion and a third portion, and the first portion of each connecting lead is electrically connected to a first bonding electrode. The electrode carrier plate is arranged on the non-display surface and provided thereon with the second bonding electrodes arranged side by side at intervals, and each second bonding electrode is electrically connected to a third portion of a connecting lead.

A display apparatus may include a plurality of pixels in a display area and a pixel comprises a plurality of sub-pixels, a plurality of first electrodes that extend in a first direction and are between the sub-pixels, a connection electrode between the plurality of first electrodes and configured to transmit a voltage, and a second electrode connected to the connection electrode and configured to apply the voltage to the plurality of sub-pixels.

An embodiment of the present disclosure provides a semiconductor device arrangement. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

A display panel and a display apparatus. The display panel includes a main display area, a first secondary display area, a second secondary display area and a transition display area, a transmittance of the first secondary display area is greater than a transmittance of the main display area, and the display panel includes: a first pixel unit located in the first secondary display area and including a first sub-pixel; a second pixel unit located in the second secondary display area and including a second sub-pixel; and a third pixel unit located in the transition display area and including a third sub-pixel, in which at least two of the first sub-pixel, the second sub-pixel and the third sub-pixel of a first color have a first size.

Provided is a composition containing nanoparticles, nanorods, and nanowires that do not essentially require a carrier such as a substrate. The composition contains nanoparticles, nanorods, and nanowires, and the nanoparticles, the nanorods, and the nanowires are each formed of at least one of Si or SiO.