The display device according to the embodiment may include a substrate, a first planarization layer containing the first opening on the substrate, a first assembly wiring and a second assembly wiring arranged spaced apart from each other inside the first opening and on the first planarization layer, a second planarization layer covering a portion of the first assembly wiring and the second assembly wiring and including a second opening, a light emitting device disposed inside the second opening, wherein the first electrode overlaps the first assembly wiring and the second assembly wiring, and an insulation layer covering the first assembly wiring or second assembly wiring placed inside the first opening Insulation layer covering the first assembly wiring or second assembly wiring placed inside the first opening, and the first electrode is bonded to one of the first assembly wiring and the second assembly wiring.

A multi-coordinate system calibration and equipment alignment method includes: determining a first mapping relationship between a first image pixel coordinate system of an intermediate carrier substrate carrying stage and a world coordinate system; determining a second mapping relationship between a second image pixel coordinate system of a backplane carrying stage and the world coordinate system; determining galvanometer start point coordinates in the world coordinate system; obtaining first template calibration coordinates in the world coordinate system by using the first mapping relationship and the galvanometer start point coordinates; obtaining second template calibration coordinates in the world coordinate system by using the second mapping relationship and the galvanometer start point coordinates; aligning the intermediate carrier substrate based on actual coordinates of the intermediate carrier substrate carrying stage and the first template calibration coordinates; and aligning the backplane based on actual coordinates of the backplane carrying stage and the second template calibration coordinates.

A multi-coordinate system calibration and equipment alignment method includes: determining a first mapping relationship between a first image pixel coordinate system of an intermediate carrier substrate carrying stage and a world coordinate system; determining a second mapping relationship between a second image pixel coordinate system of a backplane carrying stage and the world coordinate system; determining galvanometer start point coordinates in the world coordinate system; obtaining first template calibration coordinates in the world coordinate system by using the first mapping relationship and the galvanometer start point coordinates; obtaining second template calibration coordinates in the world coordinate system by using the second mapping relationship and the galvanometer start point coordinates; aligning the intermediate carrier substrate based on actual coordinates of the intermediate carrier substrate carrying stage and the first template calibration coordinates; and aligning the backplane based on actual coordinates of the backplane carrying stage and the second template calibration coordinates.

The display device can include a substrate, a first assembling wiring on the substrate, a second assembling wiring on the first assembling wiring, an insulating layer between the first assembling wiring and the second assembling wiring, a partition wall disposed on the second assembling wiring and having an assembly hole, and a semiconductor light-emitting device in the assembly hole. A part of the second assembling wiring can be disposed at a center of the assembly hole, and a width of a part of the second assembling wiring can be smaller than a diameter of the assembly hole.

A display substrate, including a first substrate and a backplane arranged in a sequentially laminated manner, and a light-emitting layer, where the light-emitting layer includes a binding pads and a light-emitting elements arranged one-to-one corresponding to each other, where the binding pad is arranged on a side of the backplane away from the first substrate, and a pin of the light-emitting element is electrically connected to the binding pad, where the binding pad includes a first region and a second region, the orthographic projection of the first region on the backplane is covered by the orthographic projection of the light-emitting element on the backplane, and the orthographic projection of the second region on the backplane is arranged on the outer side of the orthographic projection of the light-emitting element on the backplane.

A display substrate, including a first substrate and a backplane arranged in a sequentially laminated manner, and a light-emitting layer, where the light-emitting layer includes a binding pads and a light-emitting elements arranged one-to-one corresponding to each other, where the binding pad is arranged on a side of the backplane away from the first substrate, and a pin of the light-emitting element is electrically connected to the binding pad, where the binding pad includes a first region and a second region, the orthographic projection of the first region on the backplane is covered by the orthographic projection of the light-emitting element on the backplane, and the orthographic projection of the second region on the backplane is arranged on the outer side of the orthographic projection of the light-emitting element on the backplane.

A transfer method for micro flip chips includes forming a first bonding member on a surface of one side of a second electrical connection piece of each of a plurality of micro flip chips facing away from a temporary substrate to which they are adhered. The micro flip chips are transferred onto a drive substrate. The second electrical connection pieces of the micro flip chips are connected to a corresponding one of first electrical connection pieces of the drive substrate via the first bonding members. The micro flip chips are inspected to determine bad point positions of defective chips on the drive substrate. The first bonding member is irradiated at each bad point position by laser and the defective chip is removed. The method ensures stable bonding between the micro flip chips and the drive substrate and prevents the first electrical connection pieces from being damaged by laser irradiation.

A transfer method for micro flip chips includes forming a first bonding member on a surface of one side of a second electrical connection piece of each of a plurality of micro flip chips facing away from a temporary substrate to which they are adhered. The micro flip chips are transferred onto a drive substrate. The second electrical connection pieces of the micro flip chips are connected to a corresponding one of first electrical connection pieces of the drive substrate via the first bonding members. The micro flip chips are inspected to determine bad point positions of defective chips on the drive substrate. The first bonding member is irradiated at each bad point position by laser and the defective chip is removed. The method ensures stable bonding between the micro flip chips and the drive substrate and prevents the first electrical connection pieces from being damaged by laser irradiation.

In an embodiment an arrangement includes a plurality of optoelectronic semiconductor components arranged in a common plane, wherein each semiconductor component is laterally delimited by side faces, and wherein each semiconductor component has a semiconductor body with an active region configured to emit electromagnetic radiation, a radiation outlet side configured to couple out the electromagnetic radiation, a rear face opposite to the radiation outlet side, and a contact structure arranged on the rear face. The arrangement further includes an output element, an electrically insulating insulation layer and an electrical connection structure, wherein the insulation layer is arranged between side faces of adjacent semiconductor components and is absorbent or reflective of the electromagnetic radiation.

In an embodiment an arrangement includes a plurality of optoelectronic semiconductor components arranged in a common plane, wherein each semiconductor component is laterally delimited by side faces, and wherein each semiconductor component has a semiconductor body with an active region configured to emit electromagnetic radiation, a radiation outlet side configured to couple out the electromagnetic radiation, a rear face opposite to the radiation outlet side, and a contact structure arranged on the rear face. The arrangement further includes an output element, an electrically insulating insulation layer and an electrical connection structure, wherein the insulation layer is arranged between side faces of adjacent semiconductor components and is absorbent or reflective of the electromagnetic radiation.