Method and structure for shielding electromagnetic interference in photonic integrated circuits (PIC) disposed on electronic integrated circuits (EIC). The invention addresses the electromagnetic interference problem by employing vias through the PIC's bulk silicon substrate. The invention also uses a conductive layer covering the backside of the PIC bulk silicon substrate on which the metal heat spreader can be placed. Now, the vias can make electrical contact from the reference net formed for PIC's light transmission component on one or more metal layers of the PIC to the conductive layer on the backside of the PIC. Such an arrangement allows for robust electrical connection and allows the metal heat spreader to act as robust ground thus terminating the electromagnetic fields.

Provided is a light-emitting device including a body including a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode and a second electrode provided on a first surface of the body, the first electrode and the second electrode being in contact with the first semiconductor layer and the second semiconductor layer, respectively, and a third electrode and a fourth electrode provided on a second surface of the body, the third electrode and the fourth electrode being in contact with the first semiconductor layer and the second semiconductor layer, respectively.

An integrated circuit package includes a substrate having a first surface and a second surface. An electronic integrated circuit chip has a first surface and a second surface, with the second surface mounted on the first surface of the substrate. A preformed glass cover is assembled on the first surface of the substrate and arranged to contain the electronic integrated circuit chip.

An integrated circuit package includes a substrate having a first surface and a second surface. An electronic integrated circuit chip has a first surface and a second surface, with the second surface mounted on the first surface of the substrate. A preformed glass cover is assembled on the first surface of the substrate and arranged to contain the electronic integrated circuit chip.

A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising at least one electromagnetic wave receiver, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said device comprises at least one read out circuit, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.

A photosensitive chip, a manufacturing method thereof, and a photosensitive module are provided. The photosensitive chip includes an isosceles trapezoid body, a positive electrode, and a negative electrode. The isosceles trapezoid body comprises an N-type semiconductor layer and a P-type semiconductor layer. The P-type semiconductor layer is disposed adjacent to the N-type semiconductor layer. The positive electrode is electrically connected to the P-type semiconductor layer, and the negative electrode is electrically connected to the N-type semiconductor layer.

A photosensitive chip, a manufacturing method thereof, and a photosensitive module are provided. The photosensitive chip includes an isosceles trapezoid body, a positive electrode, and a negative electrode. The isosceles trapezoid body comprises an N-type semiconductor layer and a P-type semiconductor layer. The P-type semiconductor layer is disposed adjacent to the N-type semiconductor layer. The positive electrode is electrically connected to the P-type semiconductor layer, and the negative electrode is electrically connected to the N-type semiconductor layer.

A light-emitting device includes a light-emitting element having first to fourth outer edges and including: an inner light-emitting portion including an inner semiconductor structure and inner electrodes; and an outer light-emitting portion surrounding an entire periphery of the inner light-emitting portion in the plan view and including an outer semiconductor structure, a first outer electrode including first to fourth extending portion respectively extending along the first outer edge, one of the third and fourth outer edges, the second outer edge, and the other of the third and fourth outer edges. An outermost surface of the light-emitting element includes surfaces of the inner and outer semiconductor structures. In the plan view, a first gap is between end portions of the first and fourth extending portions, and a second gap is between end portions of the second and third extending portions.

A light-emitting device includes a light-emitting element having first to fourth outer edges and including: an inner light-emitting portion including an inner semiconductor structure and inner electrodes; and an outer light-emitting portion surrounding an entire periphery of the inner light-emitting portion in the plan view and including an outer semiconductor structure, a first outer electrode including first to fourth extending portion respectively extending along the first outer edge, one of the third and fourth outer edges, the second outer edge, and the other of the third and fourth outer edges. An outermost surface of the light-emitting element includes surfaces of the inner and outer semiconductor structures. In the plan view, a first gap is between end portions of the first and fourth extending portions, and a second gap is between end portions of the second and third extending portions.

A system in a package (SIP) (195) includes carrier layer regions (107) that have a dielectric material with a metal post (109) therethrough, where adjacent carrier layer regions define a gap. A driver IC die (110) is positioned in the gap having nodes connected to bond pads (111) exposed by openings in a top side of a first passivation layer (113), with the bond pads facing up. A dielectric layer (116) is on the first passivation layer and carrier layer region (107) that includes filled through vias (116a) coupled to the bond pads and to the metal post (109). A light blocking layer (118) is on sidewalls and a bottom of the substrate. A first device (140) includes a light emitter that has first bondable features (151a). The light blocking layer blocks at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.