An electronic device includes a first substrate, a first circuit layer, a semiconductor chip, and a transparent conductive layer. The first circuit layer is disposed on the first substrate. The semiconductor chip is disposed on the first substrate and electrically connected to the first circuit layer. The semiconductor chip includes a semiconductor die, a filling layer, and a reflective layer. The semiconductor die has a surface and another surface opposite to the surface. The filling layer surrounds the semiconductor die. The reflective layer is disposed on the filling layer and the semiconductor die. The reflective layer includes a first part and a second part. The first part is disposed on the surface of the semiconductor die. The second part is disposed on the filling layer. The conductive layer is disposed on the another surface of the semiconductor die and connects to the second part.

An electronic device includes a first substrate, a first circuit layer, a semiconductor chip, and a transparent conductive layer. The first circuit layer is disposed on the first substrate. The semiconductor chip is disposed on the first substrate and electrically connected to the first circuit layer. The semiconductor chip includes a semiconductor die, a filling layer, and a reflective layer. The semiconductor die has a surface and another surface opposite to the surface. The filling layer surrounds the semiconductor die. The reflective layer is disposed on the filling layer and the semiconductor die. The reflective layer includes a first part and a second part. The first part is disposed on the surface of the semiconductor die. The second part is disposed on the filling layer. The conductive layer is disposed on the another surface of the semiconductor die and connects to the second part.

The present disclosure provides a display apparatus, a display panel and a method of preparing the same. A display panel includes: a base substrate; and a plurality of light-emitting units provided on the base substrate, where each of the light-emitting units includes a first electrode, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a second electrode which are stacked, the first electrode is provided on a side of the second electrode facing away from the base substrate, and the plurality of light-emitting units share a common first electrode. The present disclosure can improve display resolution.

Provided are a display baseplate, a mould assembly, a spliced display module, and a display apparatus. The display baseplate includes a backplate light emitters and an encapsulation layer. The backplate includes a first main surface and a second main surface that are opposite to each other, and side surfaces connected to the first main surface and the second main surface light emitters are located on the first main surface, the encapsulation layer is at least partially located on the first main surface and covers the plurality of light emitters. The spliced display module includes a splicing units, the splicing units each include a splicing frame and a display baseplate, the display baseplate is fixed on the splicing frame with the light emitters away from the splicing frame; and the splicing frames of adjacent splicing units are spliced together. The display apparatus includes a display baseplate or a spliced display module.

A chip structure includes a chip wafer unit and a color conversion substrate unit disposed on a light-exit side of the chip wafer unit. The chip wafer unit includes a light-emitting layer and an electrode layer sequentially stacked in a first direction. The light-emitting layer includes light-emitting portions. Each light-emitting portion includes at least two light-emitting sub-portions. The electrode layer includes a cathode, connection electrodes, and anodes in one-to-one correspondence with the light-emitting portions. The at least two light-emitting sub-portions are sequentially connected through at least one connection electrode. Among the at least two light-emitting sub-portions sequentially connected, a first one light-emitting sub-portion is a first selected light-emitting sub-portion, and a last one light-emitting sub-portion is a second selected light-emitting sub-portion. The first selected light-emitting sub-portion is connected to the cathode, and the second selected light-emitting sub-portion is connected to an anode.

A chip structure includes a chip wafer unit and a color conversion substrate unit disposed on a light-exit side of the chip wafer unit. The chip wafer unit includes a light-emitting layer and an electrode layer sequentially stacked in a first direction. The light-emitting layer includes light-emitting portions. Each light-emitting portion includes at least two light-emitting sub-portions. The electrode layer includes a cathode, connection electrodes, and anodes in one-to-one correspondence with the light-emitting portions. The at least two light-emitting sub-portions are sequentially connected through at least one connection electrode. Among the at least two light-emitting sub-portions sequentially connected, a first one light-emitting sub-portion is a first selected light-emitting sub-portion, and a last one light-emitting sub-portion is a second selected light-emitting sub-portion. The first selected light-emitting sub-portion is connected to the cathode, and the second selected light-emitting sub-portion is connected to an anode.

In an embodiment an arrangement includes a plurality of optoelectronic semiconductor components arranged in a common plane, wherein each semiconductor component is laterally delimited by side faces, and wherein each semiconductor component has a semiconductor body with an active region configured to emit electromagnetic radiation, a radiation outlet side configured to couple out the electromagnetic radiation, a rear face opposite to the radiation outlet side, and a contact structure arranged on the rear face. The arrangement further includes an output element, an electrically insulating insulation layer and an electrical connection structure, wherein the insulation layer is arranged between side faces of adjacent semiconductor components and is absorbent or reflective of the electromagnetic radiation.

In an embodiment an arrangement includes a plurality of optoelectronic semiconductor components arranged in a common plane, wherein each semiconductor component is laterally delimited by side faces, and wherein each semiconductor component has a semiconductor body with an active region configured to emit electromagnetic radiation, a radiation outlet side configured to couple out the electromagnetic radiation, a rear face opposite to the radiation outlet side, and a contact structure arranged on the rear face. The arrangement further includes an output element, an electrically insulating insulation layer and an electrical connection structure, wherein the insulation layer is arranged between side faces of adjacent semiconductor components and is absorbent or reflective of the electromagnetic radiation.

A driving backplane includes a substrate, a plurality of pad groups, and a plurality of marks. The plurality of pad groups and the plurality of marks are located on a same side of the substrate, a pad group includes at least one pad, and orthogonal projections of the plurality of marks on the substrate and orthogonal projections of the plurality of pad groups on the substrate have no overlap. The pad group corresponds to at least one mark. An orthogonal projection of the at least one mark on the substrate is located on a circumference of an orthogonal projection of a corresponding area of the pad group on the substrate, is adjacent to an orthogonal projection of the pad group on the substrate, and has a first gap from the orthogonal projection of the pad group on the substrate.

A driving backplane includes a substrate, a plurality of pad groups, and a plurality of marks. The plurality of pad groups and the plurality of marks are located on a same side of the substrate, a pad group includes at least one pad, and orthogonal projections of the plurality of marks on the substrate and orthogonal projections of the plurality of pad groups on the substrate have no overlap. The pad group corresponds to at least one mark. An orthogonal projection of the at least one mark on the substrate is located on a circumference of an orthogonal projection of a corresponding area of the pad group on the substrate, is adjacent to an orthogonal projection of the pad group on the substrate, and has a first gap from the orthogonal projection of the pad group on the substrate.