A method is disclosed of fabricating a MEMS device that includes one or more wafers configured as pump or valve. The pump or valve includes an inlet port to receive fluid and an outlet port to release the fluid within the pump or valve. The method comprises growing silicon dioxide on a silicon layer of the one or more wafers to form a silicon dioxide layer on the silicon layer, depositing silicon nitride on the silicon dioxide layer of the one or more wafers to form a silicon nitride layer on the silicon dioxide layer, spinning a front side to create a pattern thereon defining an area for the pump or valve, dry etching the one or more wafers at the area for the pump or valve to remove the silicon dioxide and silicon nitride layers to define an opening for the pump or valve.

A piezoelectric element includes: a piezoelectric body having a first surface and a second surface that are different from each other; a first electrode provided at the first surface; and a second electrode provided at the second surface. The piezoelectric body contains a helical chiral polymer crystal having an orientation axis as a crystal axis, the orientation axis is uniaxially oriented in a manner of intersecting both the first surface and the second surface, and a degree of orientation of the orientation axis in the piezoelectric body is 0.80 or more.

Provided is a method for preparing an organic electronic device, comprising steps of: applying an ink composition on a substrate, on which an organic electronic element is formed; applying heat thereto before curing the applied ink composition; and curing the applied ink composition by irradiating with light having a wavelength in a range of 300 nm to 450 nm. Also provided is an organic electronic device, comprising a substrate, an organic electronic element formed on the substrate, and an organic layer sealing the entire surface of the organic electronic element, wherein after the organic layer is maintained at 110° C. for 30 minutes, the out-gas amount measured using Purge & Trap-gas chromatography/mass spectrometry is less than 150 ppm.

Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.

A technique, comprising: forming in situ on a support substrate: a first metal layer; a light-absorbing layer after the first metal layer; a conductor pattern after the light-absorbing layer; and a semiconductor layer after the conductor pattern; patterning the semiconductor layer using a resist mask to form a semiconductor pattern defining one or more semiconductor channels of one or more semiconductor devices; and patterning the light-absorbing layer using the resist mask and the conductor pattern, so as to selectively retain the light-absorbing layer in regions that are occupied by at least one of the resist mask and the conductor pattern.

A method for manufacturing an organic memory device is disclosed. According to one embodiment, the method comprises the steps of: forming a first electrode on a substrate; forming an organic active layer on the first electrode; and forming a second electrode on the organic active layer through an orthogonal photolithography technique using a fluorinated material.

A flexible array substrate structure and manufacturing method thereof are disclosed, in which the patterning process of an organic semi-conductive layer is achieved by using the inside wall of the opening of a color film layer as a bank, so that one mask can be saved. Also, a process for manufacturing a device can be simplified by an improved device structure, so that the flexible array substrate structure of the invention can be obtained by only using four masks.

Provided is a display device including a substrate having a first region and a second region adjacent to the first region. The second region is located in a direction from the first region to an outside of the substrate. The first region possesses a transistor, a leveling film over the transistor, and a light-emitting element over the leveling film and electrically connected to the transistor. The display device further includes a plurality of metal films in the second region and a sealing film. The plurality of metal films includes at least one of Group 1 metal elements and Group 2 elements, and the leveling film is arranged so as to be confined in the first region.

An integrated circuit transformer (150) is formed with a primary winding (91) located in at least a first winding layer having a first thickness, a secondary winding (92) located in at least the first winding layer and having a first center point at the first side of the transformer and two secondary terminals at a second, opposite side of the transformer, and a first center tap feed line (81) located along a symmetry axis of the transformer in an upper metal layer having a second thickness that is at least equivalent to the first thickness of the first winding layer, wherein the first center tap feed line has a direct electrical connection to the first center point in the secondary winding.

Provided is a friction nano power generation synaptic transistor. The friction nano power generation synaptic transistor includes a friction nano generator, a synaptic transistor, a substrate, an electrode layer formed on the substrate, a shared intermediate layer formed on the electrode layer; a synaptic transistor active layer, a source electrode, and a drain electrode which are formed on the shared intermediate layer; and a positive friction layer and a negative friction layer formed on the shared intermediate layer, where the shared intermediate layer is used as a dielectric layer of the synaptic transistor and an intermediate layer of the friction nano generator.