A semiconductor device according to an embodiment of the present disclosure includes a substrate, a resistance change layer disposed on the substrate and including a plurality of carbon nanostructures, a channel layer disposed on the resistance change layer, a gate electrode layer disposed on the channel layer, and a source electrode layer and a drain electrode layer disposed to contact portions of the channel layer.

A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

An organic molecular memory of embodiments includes: a first electrode; a second electrode; an organic molecular layer provided between the first electrode and the second electrode, extending in a first direction from the first electrode toward the second electrode, and containing a first molecule and a second molecule provided between the first molecule and the second electrode; and a third electrode facing the second molecule.

Disclosed are a memristor device, a method of fabricating the same, a synaptic device including a memristor device, and a neuromorphic device including a synaptic device. The disclosed memristor device may comprise a first electrode, a second electrode disposed to be spaced apart from the first electrode; and a resistance changing layer including a copolymer between the first electrode and the second electrode. The copolymer may be a copolymer of a first monomer and a second monomer, and the first polymer formed from the first monomer may have a property that diffusion of metal ions is faster than that of the second polymer formed from the second monomer. The second polymer may have a lower diffusivity of metal ions as compared with the first polymer. The first monomer may include vinylimidazole (VI). The second monomer may include 1,3,5-trivinyl-1,3,5-trimethylcyclotrisiloxane (V3D3). The copolymer may include p(V3D3-co-VI).

A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.

An optical detector (110) is disclosed. The optical detector (110) comprises: an optical sensor (112), having a substrate (116) and at least one photosensitive layer setup (118) disposed thereon, the photosensitive layer setup (118) having at least one first electrode (120), at least one second electrode (130) and at least one photovoltaic material (140) sandwiched in between the first electrode (120) and the second electrode (130), wherein the photovoltaic material (140) comprises at least one organic material, wherein the first electrode (120) comprises a plurality of first electrode stripes (124) and wherein the second electrode (130) comprises a plurality of second electrode stripes (134), wherein the first electrode stripes (124) and the second electrode stripes (134) intersect such that a matrix (142) of pixels (144) is formed at intersections of the first electrode stripes (124) and the second electrode stripes (134); and at least one readout device (114), the readout device (114) comprising a plurality of electrical measurement devices (154) being connected to the second electrode stripes (134) and a switching device (160) for subsequently connecting the first electrode stripes (124) to the electrical measurement devices (154).

A thin-film transistor array includes a substrate and thin-film transistors positioned in matrix on the substrate. The thin-film transistors each include source and drain electrodes formed on a gate insulation layer, and a semiconductor layer formed on the gate insulation layer and positioned between the source and drain electrodes. The semiconductor layer is formed in stripes over the plurality of thin-film transistors such that one of the stripes has a long axis direction coinciding with a channel width direction of one of the thin-film transistors. The semiconductor layer has a cross section in a short axis direction of the stripe such that a thickness of the semiconductor layer gradually decreases outwardly from a center portion of the stripe.

The invention discloses an organic electric memory device based on phosphonic acid or trichlorosilane-modified ITO glass substrate and a preparation method thereof. The preparation method comprises the following steps of 1) cleaning the ITO glass substrate; 2) forming a phosphonic acid or trichlorosilane modified layer; 3) forming an organic coating film layer; and 4) forming an electrode, and finally obtaining the organic electric memory device. By adoption of the method, a series of sandwich-type organic electric memory devices are prepared; meanwhile, the preparation method is simple, convenient, fast, and easy to operate; compared with the conventional device, the turn-on voltage of the organic electric memory device is lowered, the yield of the multi-level system is improved, and the problem of relatively low ternary productivity at present is solved; and therefore, the organic electric memory device has extremely high application value in the future memory fields.