A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.

Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

Methods for manufacturing memory resistor devices and memory resistor devices manufactured according to such methods. A method includes depositing a first layer of dielectric material onto a substrate comprising a first electrode; bombarding the deposited first layer with an ion beam to create one or more defects in the first layer; depositing a second electrode such that the deposited first layer is between the first electrode and the second electrode; electroforming the first layer by applying an electroforming voltage between the first electrode and the second electrode.

A semiconductor device that includes: first conductive lines; second conductive lines disposed over the first lines to be spaced apart from the first lines; and a selector layer disposed between the first lines and the second lines and including a dielectric material and a dopant doped with a uniform dopant profile.

According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.

A semiconductor memory may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer separated from the first electrode layer, wherein the first and second electrode layers are coupled to receive a voltage applied to the first and second electrode layers; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and configured to store data and operable to disconnect or connect a conducting path between the first electrode layer and the second electrode layer, to respond to the voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes an insulating material layer, a first dopant that creates a shallow trap providing a path for conductive carriers in the insulating material layer, and a second dopant that is movable in the insulating material layer according to a polarity of the voltage applied to the first and second electrode layers.

A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. Forming the first unit switching layer includes forming a first unit insulation layer, and injecting first dopants into the first unit insulation layer by performing a first ion implantation process. Forming the second unit switching layer includes forming a second unit insulation layer, and injecting second dopants into the second unit insulation layer by performing a second implantation process.

A method of manufacturing a switching element includes forming a pillar-shaped structure over a substrate, performing a dopant injection process to form a first doping region in an insulation layer. The method further includes performing the dopant injection process to form a second doping region in a first electrode, to form a third doping region in a second electrode, or both. The pillar-shaped structure includes the first electrode, the insulation layer, and the second electrode that are disposed over a substrate. The first and second doping regions form a first interface therebetween, and the first and third doping regions form a second interface therebetween. The first doping region corresponds to a region in which a threshold switching operation region is performed.

Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) such as in a CEM device capable of switching between and/or among impedance states. In particular embodiments, a CEM may be formed from one or more transition metal oxides (TMOs), one or more post transition metal oxides (PTMOs) or one or more post transition metal chalcogenides (PTMCs), or a combination thereof.