Provided is a memory device and an electronic device including the same. The memory device according to an example embodiment may include: a two-dimensional material layer including a two-dimensional material; a contact region in contact with an edge of the two-dimensional material layer; and an electrode which is electrically connected to the contact region and changes a domain of a region adjacent to the contact region of the two-dimensional material layer by an applied voltage.

A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

This invention relates to memtransistors, fabricating methods and applications of the same. The memtransistor includes a polycrystalline monolayer film of an atomically thin material. The polycrystalline monolayer film is grown directly on a sapphire substrate and transferred onto an SiO.sub.2/Si substrate; and a gate electrode defined on the SiO.sub.2/Si substrate; and source and drain electrodes spatially-apart formed on the polycrystalline monolayer film to define a channel region in the polycrystalline monolayer film therebetween. The gate electrode is capacitively coupled with the channel region.

A memory structured in lines and columns over several superimposed levels, each level comprising an array of memory elements and gate-all-around access transistors, each transistor including a semiconductor nanowire and each gate being insulated from the gates of the other levels, further comprising: conductive portions, each crossing at least two levels and coupled to first ends of the nanowires of one column of the levels; memory stacks, each crossing the levels and coupled to second ends of the nanowires of said column; first conductive lines, each connected to the conductive portions of the same column; word lines each extending in the same level while coupling together the gates of the same line and located in said level.

Various embodiments may provide an electronic synapse device. The electronic synapse device may include a body including a doped chalcogenide layer including a chalcogenide material and a dopant. The electronic synapse device may also include a drain electrode in contact with the body. The electronic synapse device may further include a source electrode in contact with the body. The electronic synapse device may additionally include a gate electrode including an electrode contact layer in contact with the doped chalcogenide layer. The electrode contact layer may be any one selected from a group consisting of an electrically conductive layer including an electrically conductive material and a dopant layer including the dopant.

A routing structure is disclosed. A first wiring line coupled to a programming access device and a routing block driver and receiver enabling device and a second wiring line coupled to a programming access device and a routing block driver and receiver enabling device. An insulator-metal-transistor device that includes a top electrode, a middle electrode and a bottom electrode, coupled at the intersection of the first wiring line and the second wiring line.

Synaptic resistors (synstors), and their method of manufacture and integration into exemplary circuits are provided. Synstors are configured to emulate the analog signal processing, learning, and memory functions of synapses. Circuits incorporating synstors are capable of performing signal processing and learning concurrently in parallel analog mode with speed, energy efficiency, and functions superior to computers.

Disclosed is a three-terminal electro-chemical memory cell with a vertical structure for neuromorphic computation, including a circumferential hole, first and second conductive electrode layers sequentially stacked along an outer surface of the circumferential hole, an electrolyte layer formed along an inner surface of the circumferential hole and connected to one end of each of the first and second conductive electrode layers, and a gate electrode disposed parallel to the electrolyte layer in an inner surface direction of the circumferential hole.

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Techniques for fabricating a volatile memory structure having a transistor and a memory component is described. The volatile memory structure comprises the memory component formed on a substrate, wherein a first shape comprising one or more pointed edges is formed on a first surface of the memory component. The volatile memory structure further comprises transistor formed on the substrate and electrically coupled to the memory component to share operating voltage, wherein operating voltage applied to the transistor flows to the memory component.