Provided is a three-dimensional vertical memory device including: a semiconductor substrate, a vertical columnar channel region provided on the semiconductor substrate and having a void of a predetermined size therein; a source electrode and a drain electrode spaced apart from each other with the channel region interposed therebetween; and a gate stack formed on the channel region.

An electrical device comprising a reconfigurable integrated circuit that includes paired top electrodes and bottom electrodes separated from each other by an active layer.

Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

An electrolyte-based field effect transistor includes a dielectric layer; a source electrode and a drain electrode located on top of the dielectric layer; the electrolyte-based transistor further including an electrolyte layer between and on top of the source electrode and the drain electrode, the part of the electrolyte layer located between the source electrode and the drain electrode being in direct contact with the dielectric layer; and a gate electrode on top of the electrolyte layer, the orthogonal projection of the gate electrode in a plane including the source and drain electrodes being located, at least in part, between the source and the drain electrodes.

Embodiments of the present application relate to a resistive memory device and a preparation method thereof. The preparation method includes: providing a base; forming bit line trenches in the base; forming a resistive material layer on a sidewall and the bottom of the bit line trench; and forming a bit line structure in the bit line trench through filling, wherein a variable resistor structure includes the bit line structure and the resistive material layer.

A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

Selector switch provided with: a structure based on at least one phase change material placed between a first conducting element and a second conducting element, the phase change material being capable of changing state, means of heating the phase change material provided with at least one first heating electrode and at least one other heating electrode, the structure based on a phase change material being configured to form a confined active zone of the phase change material at a distance from the conducting elements.

A three-dimensional resistive random access memory structure includes a base layer, a first layer, a second layer, a third layer and a fourth layer. The first layer includes two first conductive layers and a first via. One of the two first conductive layers is electrically connected between the base layer and the first via. The second layer includes three second conductive layers and two second vias. Two first resistive elements are formed between one of the two second vias and two of the three second conductive layers. The third layer includes three third conductive layers and two third vias. Two second resistive elements are formed between one of the two third vias and two of the three third conductive layers. The fourth layer includes a fourth conductive layer. The fourth conductive layer is electrically connected to the two third vias.

A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.