This invention relates to memtransistors, fabricating methods and applications of the same. The memtransistor includes a polycrystalline monolayer film of an atomically thin material. The polycrystalline monolayer film is grown directly on a sapphire substrate and transferred onto an SiO.sub.2/Si substrate; and a gate electrode defined on the SiO.sub.2/Si substrate; and source and drain electrodes spatially-apart formed on the polycrystalline monolayer film to define a channel region in the polycrystalline monolayer film therebetween. The gate electrode is capacitively coupled with the channel region.

Disclosed is a tunable inductor device having a substrate, a planar spiral conductor having a plurality of spaced-apart turns disposed over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate between and in contact with a pair of adjacent segments of the plurality of spaced-apart turns, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

A memory structured in lines and columns over several superimposed levels, each level comprising an array of memory elements and gate-all-around access transistors, each transistor including a semiconductor nanowire and each gate being insulated from the gates of the other levels, further comprising: conductive portions, each crossing at least two levels and coupled to first ends of the nanowires of one column of the levels; memory stacks, each crossing the levels and coupled to second ends of the nanowires of said column; first conductive lines, each connected to the conductive portions of the same column; word lines each extending in the same level while coupling together the gates of the same line and located in said level.

The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices with an electrode having tapered sides. The present disclosure provides a memory device including a first electrode having a tapered shape and including a tapered side, a top surface, and a bottom surface, in which the bottom surface has a larger surface area than the top surface, a resistive layer on and conforming to at least the tapered side of the first electrode, and a second electrode laterally adjacent to the tapered side of the first electrode, the second electrode including a top surface and a side surface abutting the resistive layer, in which the side surface forms an acute angle with the top surface.

Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

A method of forming a phase change switching device includes providing a substrate, forming first and second RF terminals on the substrate, forming a strip of phase change material on the substrate that is connected between the first and second RF terminals, forming a heating element adjacent to the strip of phase change material such that the heating element is configured to control a conductive state of the strip of phase change material. The first and second RF terminals and the heating element are formed by a lithography process that self-aligns the heating element with the first and second RF terminals

The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.

A resistive RAM module comprises a source electrode and an intermediate electrode that is formed on the source electrode. The intermediate electrode has a closed-curve profile. The resistive RAM module also comprises a memristor element that is deposited on the intermediate electrode. The resistive RAM module also comprises a sink electrode that is in contact with the memristor element. The intermediate electrode is electrically between the source electrode and the memristor element and the memristor element is electrically between the intermediate electrode and the sink electrode.

Provided is a memory device including a stack structure, a plurality of channel layers, a source line, a bit line, a switching layer, and a dielectric pillar. The stack structure has a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The channel layers are respectively embedded in the conductive layers. The source line penetrates through the stack structure to be electrically connected to the channel layers at first sides of the channel layers. The bit line penetrates through the stack structure to be coupled to the channel layers at second sides of the channel layers. The switching layer wraps the bit line to contact the channel layers at the second sides of the channel layers. The dielectric pillar penetrates through the channel layers to divide each channel layer into a doughnut shape. A method of manufacturing a memory device is also provided.