A memristor material is disclosed which has the chemical formula R.sub.1-xA.sub.xB0.sub.3, wherein R is one of Eu, Gd, Tb, Nd, A is one of Ca, Sr, Ba, B is one of Mn, Co, Ni, and x is larger than 0 but smaller than 1, a preferred example being Gd.sub.1-xCa.sub.xMn0.sub.3 (GCMO) with x not less than 0.2 to obtain practical resistance switching ratios. A memristor can be manufactured by pulsed laser deposition using a sintered target of said material.

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a bottom electrode and a top electrode separated by a dielectric film. A portion of the dielectric film directly above the bottom electrode may be doped and crystalline. The semiconductor structure may include a stud below and in electrical contact with the bottom electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

A memory device includes a plurality of first conductive lines on a substrate and extending in a first direction, a plurality of second conductive lines on the plurality of first conductive lines and extending in a second direction intersecting the first direction, and a plurality of memory cells respectively between the plurality of first conductive lines and the plurality of second conductive lines. Each of the plurality of memory cells includes a switching element and a variable resistance material layer. The switching element includes a material having a composition of [Ge.sub.X P.sub.Y Se.sub.Z].sub.(1-W) [O].sub.W, where 0.15≤X≤0.50, 0.15≤Y≤0.50, 0.35≤Z≤0.70, and 0.01≤W≤0.10.

A semiconductor memory device includes a first interconnect, a second interconnect, a first storage layer, and a first insulating film. The first insulating film is provided along a surface of a part of the second interconnect and a surface of the first storage layer. The first insulating film is composed of Si, N, and O. The atomic ratio (N/O) between N and O in the first insulating film is not less than 1.0 at a first position which is the position of the second interconnect-side end surface of the first storage layer in a third direction. The atomic ratio (N/O) between N and O in the first insulating film is less than 1.0 at a second position which is the position of the end surface of the second interconnect, opposite to the first storage layer-side end surface, in the third direction.

An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Provided are a switching device and a memory device including the switching device. The switching device includes first and second electrodes, and a switching material layer provided between the first and second electrodes and including a chalcogenide. The switching material layer includes a core portion and a shell portion covering a side surface of the core portion. The switching layer includes a material having an electrical resistance greater than an electrical resistance of the core portion, for example in at least one of the core portion or the shell portion.

A device for implementing spike-timing-dependent plasticity is provided. The device includes a phase-change element, first and second electrodes disposed respective first and second surfaces of the phase-change element. The phase-change element includes a phase-change material with an inverse resistivity characteristic. The first electrode includes a first heater element, and a first electrical insulating layer which electrically insulates the first resistive heater element from the first electrode and the phase-change element. The second electrode includes a second resistive heater element, and a second electrical insulating layer which electrically insulates the second resistive heater element from the second electrode and the phase-change element.

A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

An electronic device comprising a semiconductor memory including at least one memory element is provided. The memory element comprises: a memory area for storing data; and a selection element electrically connected to the memory area and structured to include a first electrode layer, a second electrode layer, and a selection element layer that is interposed between the first electrode layer and the second electrode layer and includes an insulating material doped with a first dopant and a second dopant to form traps for trapping charge carriers, wherein an energy level of a trap formed by the first dopant is greater than an energy level of a trap formed by the second dopant.